Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
MMA8652FC
Sensors
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
9
2.4
I
2
C interface characteristic
Figure 4. I
2
C slave timing diagram
Table 6. I
2
C slave timing values
(1)
1. All values referred to VIH(min) (0.3 VDD) and VIL(max) (0.7 VDD) levels.
Parameter
Symbol
I
2
C Fast Mode
Unit
Min
Max
SCL clock frequency
f
SCL
0
400
kHz
Bus-free time between STOP and START condition
t
BUF
1.3
s
(Repeated) START hold time
t
HD;STA
0.6
s
Repeated START setup time
t
SU;STA
0.6
s
STOP condition setup time
t
SU;STO
0.6
s
SDA data hold time
t
HD;DAT
0.05
0.9
(2)
2. This device does not stretch the LOW period (tLOW) of the SCL signal.
s
SDA setup time
t
SU;DAT
100
ns
SCL clock low time
t
LOW
1.3
s
SCL clock high time
t
HIGH
0.6
s
SDA and SCL rise time
t
r
20 + 0.1 C
b
(3)
3. C
b
= total capacitance of one bus line in pF.
300
ns
SDA and SCL fall time
t
f
20 + 0.1 C
b
(3)
300
ns
SDA valid time
(4)
4. t
VD;DAT
= time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
t
VD;DAT
0.9
(2)
s
SDA valid acknowledge time
(5)
5. t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
t
VD;ACK
0.9
(2)
s
Pulse width of spikes on SDA and SCL that must be suppressed by
internal input filter
t
SP
0
50
ns
Capacitive load for each bus line
Cb
400
pF
V
IL
= 0.3 V
DD
V
IH
= 0.7 V
DD