Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

V

DDIO

Digital interface power

I

2

C/SPI_CS_B

I

2

C/SPI interface mode selection and SPI chip select pin

SCL/SCLK

I

2

C/SPI serial clock

SDA/MOSI/SPI_DIO

I

2

C serial data/SPI master serial data out slave serial data in, SPI 3-wire data In/Out (in 3-

wire SPI mode with 

CTRL_REG0[SPIW]=1)

SA0/MISO

I

2

C least significant slave device address bit/SPI master serial data in slave serial data out

To use the I

2

C interface, the I

2

C/SPI_CS_B pin should be connected to V

DDIO

. The

implemented I

2

C interface is compliant with the NXP I

2

C-bus specification for Normal

and Fast modes. The 7-bit slave addresses that may be assigned to the device are 0x20
(with SA0 = 0) and 0x21 (with SA0 = 1). When I

2

C/SPI_CS_B is high, the SA0/MISO

pin is used to define the LSB of this I

2

C address. The key timing constraints are shown

in 

SCL clock frequency

f

SCL

0

100

0

400

kHz

Bus free time between STOP and START
conditions

t

BUF

4.7

—

1.3

—

µs

Hold time (repeated) START condition

t

HD;STA

4

—

0.6

—

µs

Set-up time for a repeated START condition

t

SU;STA

4.7

—

0.6

—

µs

Set-up time for a STOP condition

t

SU;STO

4

—

0.6

—

µs

SDA data-hold time

t

HD;DAT

—

—

0.05

0.9

µs

SDA valid time

t

VD;DAT

—

3.45

—

0.9

µs

SDA valid acknowledge time

t

VD;ACK

—

3.45

—

0.9

µs

SDA setup time

t

SU;DAT

250

—

100

—

ns

SCL clock low time

t

LOW

4.7

—

1.3

—

µs

SCL clock high time

t

HIGH

—

—

0.6

—

µs

SDA and SCL rise time

t

r

—

1000

20+0.1C

b

300

ns

SDA and SCL fall time

t

f

—

300

20+0.1C

b

300

ns

Pulse width of spikes on SDA and SCL that must
be suppressed by the internal input filter

t

SP

—

50

—

50

ns

1. All values refer to VIH (min) and VIL (max) levels.

Xtrinsic 3-Axis Digital Angular Rate Gyroscope, Rev1.2, 7/2014.

Freescale Semiconductor, Inc.