Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

2. t

HD;DAT

 is the data-hold time that is measured from the falling edge of SCL, applies to data in transmission and the

acknowledge.

3. The maximum t

HD;DAT

 could be 3.45 µs and 0.9 µs for Standard mode and Fast mode, but must be less than the

maximum of t

VD;DAT

 or t

VD;ACK

 by a transition time.

4. t

VD;ACK

 = time for acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is

worse).

5. t

SU;DAT

 = maximum t

f

 for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output

stage t

f

 is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL

pins and the SDA/SCL bus lines without exceeding the maximum specified t

f

.

6. C

b

 = total capacitance of one bus line in pF.

SDA

SCL

t

SU:STA

t

HD:STA

t

SP

t

SU:STO

t

VD:ACK

70%

30%

9

th

 clock

S

P

t

BUF

Sr

There are two signals associated with the I

2

C bus: the serial clock line (SCL) and the

serial data line (SDA). The SDA is a bidirectional line used for sending and receiving
the data to/from the interface. External pull-up resistors connected to V

DDIO

 are

required for SDA and SCL. When the bus is free, both the lines are high. The I

2

C

interface is compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I

2

C

standards. Operation at frequencies higher than 400 kHz is possible, but depends on
several factors including the pull-up resistor values, and total bus capacitance (trace +
device capacitance). For more information, see 

Xtrinsic 3-Axis Digital Angular Rate Gyroscope, Rev1.2, 7/2014.

Freescale Semiconductor, Inc.