Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
3.2 General SPI Operation (4-Wire Mode)
The SPI_CS_B pin is driven low at the start of a SPI transaction, held low for the
duration of the transaction, and driven high after the transaction is complete. During a
transaction, the master toggles the SPI clock (SCLK). The SCLK polarity is defined as
having an idle value that is low and phase where data is captured on the clock's rising
edge and propagated on the falling edge.
duration of the transaction, and driven high after the transaction is complete. During a
transaction, the master toggles the SPI clock (SCLK). The SCLK polarity is defined as
having an idle value that is low and phase where data is captured on the clock's rising
edge and propagated on the falling edge.
Single read and write operations are
completed in 16 SCLK cycles or multiples of 8 cycles for multiple read/write
operations. The first SCLK cycle uses the first bit on MOSI to determine whether the
operation is a read (R/W = 1) or a write, such as R/W = 0. The following seven SCLK
cycles are the slave register addresses. SCLK cycles and are present on the MOSI line.
SCLK cycles nine through 16 are the data that is either read (present on MISO) or to
be written (present on MOSI).
operations. The first SCLK cycle uses the first bit on MOSI to determine whether the
operation is a read (R/W = 1) or a write, such as R/W = 0. The following seven SCLK
cycles are the slave register addresses. SCLK cycles and are present on the MOSI line.
SCLK cycles nine through 16 are the data that is either read (present on MISO) or to
be written (present on MOSI).
3.2.1 SPI Write (4-Wire Mode)
A write operation is initiated by transmitting a 0 for the R/W bit. Then, the 7-bit
register address, ADDR[6:0](MSB first) is encoded in the first byte. Data to be written
starts in the second serialized byte (MSB first).
register address, ADDR[6:0](MSB first) is encoded in the first byte. Data to be written
starts in the second serialized byte (MSB first).
the single write operation.
MISO
MOSI
SCLK
SPI_CS_B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W A6
A5
A4
A3
A2
A1 A0 D7 D6 D5 D4 D3 D2
D1 D0
Figure 8. SPI single write operation. R/W = 1
Multiple write operations performed similar to the single write except bytes are
written in multiples of eight SCLK cycles. The register address is auto incremented so
that every eighth next clock edges will latch the MSB of the next register. When
desired, the rising edge on SPI_CS_B stops the SPI communication.
written in multiples of eight SCLK cycles. The register address is auto incremented so
that every eighth next clock edges will latch the MSB of the next register. When
desired, the rising edge on SPI_CS_B stops the SPI communication.
1. From the Freescale SPI protocol definition, the polarity and phase settings are CPOL=0 and CPHA=0.
Digital Interfaces
Xtrinsic 3-Axis Digital Angular Rate Gyroscope, Rev1.2, 7/2014.
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