Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
MISO
MOSI
SCLK
SPI_CS_B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W A6
A5
A4
A3
A2
A1 A0 D7 D6 D5 D4 D3 D2
D1 D0
17
18
19
20
21
22
23
24
D7 D6 D5 D4 D3 D2 D1 D0
Figure 9. SPI multiple write operation showing 2 bytes written
3.2.2 SPI Single Read (4-Wire Mode)
NOTE
this description pertains only to the default SPI 4-wire
interface mode (with CTRL_REG0[SPIW] = 0). This mode is
the default out of POR, or after a hard/soft reset.
interface mode (with CTRL_REG0[SPIW] = 0). This mode is
the default out of POR, or after a hard/soft reset.
A register read operation is initiated by transmitting a 1 for the R/W bit. Then the 7-bit
register read address, A[6:0] is encoded in the first byte. The data is read from the
MISO pin (MSb first).
register read address, A[6:0] is encoded in the first byte. The data is read from the
MISO pin (MSb first).
operation.
MISO
MOSI
SCLK
SPI_CS_B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W A6
A5
A4
A3
A2
A1 A0
D7 D6 D5 D4 D3 D2
D1 D0
Figure 10. SPI single read operation. R/W = 1
Multi-byte read operations are performed similarly to single byte reads; additional bytes
are read in multiples of eight SCLK cycles. The register read address is auto
incremented by Leon-2 so that every eighth clock edge will latch the address of the next
register read address. When the desired number of bytes has been read, the rising edge
on the SPI_CS_B terminates the transaction.
are read in multiples of eight SCLK cycles. The register read address is auto
incremented by Leon-2 so that every eighth clock edge will latch the address of the next
register read address. When the desired number of bytes has been read, the rising edge
on the SPI_CS_B terminates the transaction.
Digital Interfaces
18
Xtrinsic 3-Axis Digital Angular Rate Gyroscope, Rev1.2, 7/2014.
Freescale Semiconductor, Inc.