Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

• Configurable high-pass filter cutoff frequency; Integrated Anti-Aliasing Filter

(AAF) limits output data bandwidth to ODR/2

• Embedded rate threshold detection with programmable debounce timer
• 32-sample (X/Y/Z data at 14-bit) FIFO, configurable operating mode (Circular,

Stop, Triggered)

• 2 external interrupt pins that are configurable to trigger on data-ready, rate

threshold, or FIFO events

• Self-test function for indication of device health
• Single control bit for zero-rate offset compensation

Data for each axis must be read from the respective data registers two bytes at a time;
for example, one byte for most significant byte and one byte for least significant.
Combining these two bytes results in a 16-bit 2's complement signed integer with the
sign bit in bit location #15 and the least significant bit in bit location #2. See the tables
below.

Bit

14

13

12

11

10

9

8

Data bit

D12

D11

D10

D9

D8

D7

D6

Bit

7

6

5

4

3

1

0

Data bit

D5

D4

D3

D2

D1

X

X

The conversion from counts to a dps is done by first converting the 16-bit signed
integer to 14-bit left-justified signed integer. This can be done by dividing the counts
by four, or right shifting by two, then multiplying by the appropriate sensitivity value
for the currently selected full-scale range. See 

FXAS21000 contains a 32-sample FIFO data buffer that is useful for reducing the
frequency of transactions on the I

2

C/SPI bus. The FIFO can also provide system level

power savings by allowing the host processor/MCU to go into a sleep/low-power
mode while the FXAS21000 collects up to 32 samples of 3-axis angular rate data.

Xtrinsic 3-Axis Digital Angular Rate Gyroscope, Rev1.2, 7/2014.

Freescale Semiconductor, Inc.