Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

Indicates the current status of the FIFO, when the FIFO is enabled.

When the FIFO is enabled, the STATUS register (address 0x00) also contains the
same content as this register to facilitate the emptying of the FIFO by the host
processor. The content of this register is reset upon a transition from Standby to
Active or from Ready to Active modes. The SRC_FIFO bit in the 

Bit

7

6

5

4

3

2

1

0

Read

F_OVF

F_WMKF

F_CNT[5:0]

Write

Reset

0

0

0

0

0

0

0

0

7

F_OVF

FIFO overflow flag

• A FIFO overflow event, such as when F_CNT = 32 and a new sample arrives, asserts the F_OVF

flag.

• Cleared when this register is read.

0: No overflow detected

1: Overflow detected

6

F_WMKF

FIFO watermark flag

• A FIFO sample count greater than or equal to the sample count watermark (determined by the

F_WMRK field in register 

) asserts the F_WMKF event flag.

• Disabling the FIFO clears the F_WMKF
• Cleared when this register is read.

0: No watermark detected

1: Watermark detected

5:0

F_CNT

FIFO sample counter

• Indicates the number of samples currently stored in the FIFO.
• A count value of 0b000000 indicates that the FIFO is empty.

The F_SETUP register is used to configure the FIFO. The FIFO update rate is set by
the selected system ODR (DR bits in 

Xtrinsic 3-Axis Digital Angular Rate Gyroscope, Rev1.2, 7/2014.

Freescale Semiconductor, Inc.