Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
Table 46. Device mode
Active
Ready
Device mode
0
0
Standby
0
1
Ready
1
x
Active
6.16 0x14: CTRL_REG2
This register enables and assigns the output pin(s) and logic polarities for the various
interrupt sources available on the device.
interrupt sources available on the device.
Table 47. CTRL_REG2 register
Bit
7
6
5
4
3
2
1
0
Read
INT_CFG_FIFO INT_EN_FIFO INT_CFG_RT INT_EN _RT INT_CFG_DRDY INT_EN_DRDY IPOL PP_OD
Write
Reset
0
0
0
0
0
0
0
0
Table 48. Interrupt Enable register descriptions
Register
Description
7
INT_CFG_FIFO
FIFO interrupt pin routing
0: Interrupt is routed to INT2 pin
1: Interrupt is routed to INT1 pin
6
INT_EN_FIFO
FIFO Interrupt Enable
0: FIFO interrupt disabled
1: FIFO interrupt enabled
5
INT_CFG_RT
Rate threshold interrupt pin routing
0: Interrupt is routed to INT2 pin
1: Interrupt is routed to INT1 pin
4
INT_EN_RT
Rate threshold interrupt enable
0: Rate threshold interrupt disabled
1: Rate threshold interrupt enabled
3
INT_CFG_DRDY
Data-ready interrupt pin routing
0: Interrupt is routed to INT2 pin
1: Interrupt is routed to INT1 pin
Table continues on the next page...
Register Descriptions
40
Xtrinsic 3-Axis Digital Angular Rate Gyroscope, Rev1.2, 7/2014.
Freescale Semiconductor, Inc.