Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
Table 42. TEMP register
Bit
7
6
5
4
3
2
1
0
Read
Temp[7:0]
Write
Reset
0
0
0
0
0
0
0
0
6.15 0x13: CTRL_REG1
The CTRL_REG1 register is used to configure the device ODR, set the operating mode,
and exercise the self-test and zero-rate offset adjustment functions.
and exercise the self-test and zero-rate offset adjustment functions.
NOTE
Control bits in CTRL_REG1 should be changed only in
Standby or Ready mode. Accuracy of the data is not
guaranteed if these bits are changed when the device is in
Active mode.
Standby or Ready mode. Accuracy of the data is not
guaranteed if these bits are changed when the device is in
Active mode.
Table 43. CTRL_REG1 register
Bit
7
6
5
4
3
2
1
0
Read
ZR_cond
RST
ST
DR[2:0]
Active
Ready
Write
Reset
0
0
0
0
0
0
0
0
Table 44. CTRL_REG1 field descriptions
Field
Description
7
ZR_cond
Zero-rate condition
• Used to trigger the offset compensation. For this reason, it is meant to be used only when the
device is in zero rate condition on all axes.
• Writing a 1 to this bit initiates the internal zero-rate offset calibration.
• Self-clears after the zero-rate offset calculation, and it can only be used once after a hard or soft
• Self-clears after the zero-rate offset calculation, and it can only be used once after a hard or soft
reset has occurred. In order to use the ZR_cond a second time, the device has to be reset either
with a hard or soft reset.
with a hard or soft reset.
6
RST
Software Reset
• Causes a synchronous reset of the device.
• On reset, all registers revert to their default values.
• Self cleared after assertion.
• On reset, all registers revert to their default values.
• Self cleared after assertion.
0: Device reset not triggered/completed
1: Device reset triggered
Table continues on the next page...
Register Descriptions
38
Xtrinsic 3-Axis Digital Angular Rate Gyroscope, Rev1.2, 7/2014.
Freescale Semiconductor, Inc.