Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
FXOS8700CQ
Sensors
20
Freescale Semiconductor, Inc.
5.2
SPI Interface characteristics
SPI interface is a classical master/slave serial port. The FXOS8700CQ is always considered as the slave and thus is never
initiating the communication.
initiating the communication.
and
describe the timing requirements for the SPI system.
Figure 7. SPI Timing Diagram
5.2.1
General SPI operation
NOTE
FXOS8700CQ only supports a point-to-point SPI protocol, with only one master (MCU) and
one slave device (FXOS8700CQ) present on the bus. FXOS8700CQ does not tri-state the
MISO pin when the CS_B pin is deasserted (logic high), which can lead to a bus conflict if
multiple slave devices are present on the bus.
one slave device (FXOS8700CQ) present on the bus. FXOS8700CQ does not tri-state the
MISO pin when the CS_B pin is deasserted (logic high), which can lead to a bus conflict if
multiple slave devices are present on the bus.
Do not connect more than one master and one slave device on the SPI bus.
The CS_B pin is driven low at the start of a SPI transaction, held low for the duration of the transaction, and driven high after the
transaction is complete. During a transaction the master toggles the SPI clock (SCLK) and transmits data on the MOSI pin.
transaction is complete. During a transaction the master toggles the SPI clock (SCLK) and transmits data on the MOSI pin.
A write operation is initiated by transmitting a 1 for the R/W bit. Then the 8-bit register address, ADDR[7:0] is encoded in the first
and second serialized bytes. Data to be written starts in the third serialized byte. The order of the bits is as follows:
and second serialized bytes. Data to be written starts in the third serialized byte. The order of the bits is as follows:
Byte 0: R/W,ADDR[6],ADDR[5],ADDR[4],ADDR[3],ADDR[2],ADDR[1],ADDR[0],
Byte 1: ADDR[7],X,X,X,X,X,X,X,
Byte 2: DATA[7],DATA[6],DATA[5],DATA[4],DATA[3],DATA[2],DATA[1],DATA[0].
Multiple bytes of DATA may be transmitted. The X indicates a bit that is ignored by the part. The register address is auto-
incremented so that the next clock edges will latch the data for the next register. When desired, the rising edge on CS_B stops
the SPI communication.
incremented so that the next clock edges will latch the data for the next register. When desired, the rising edge on CS_B stops
the SPI communication.
Table 11. SPI timing
Function
Symbol
Min
Max
Unit
Operating Frequency
Of
—
1
MHz
SCLK Period
tSCLK
1000
—
ns
SCLK High time
tCLKH
500
—
ns
SCLK Low time
tCLKL
500
—
ns
CS_B lead time
tSCS
65
—
ns
CS_B lag time
tHCS
65
—
ns
MOSI data setup time
tSET
25
—
ns
MOSI data hold time
tHOLD
75
—
ns
MISO data valid (after SCLK low edge)
tDDLY
—
500
ns
Width CS High
tWCS
100
—
ns
CS_B
SCLK
MOSI
MISO