Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

Sensors
Freescale Semiconductor, Inc.

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The FXOS8700CQ SPI configuration is as follows: 

•

Polarity: rising/falling

•

Phase: sample/setup

•

Order: MSB first

Data is sampled during the rising edge of SCLK and set up during the falling edge of SCLK.

A READ operation is initiated by transmitting a 0 for the R/W bit. Then the 8-bit register address, ADDR[7:0] is encoded in the 
first and second serialized bytes. Subsequent bits are ignored by the part. The read data is deserialized from the MISO pin. 

Similarly a WRITE operation is initiated by transmitting a 1 for the R/W bit. After the first and second serialized bytes multiple-
data bytes can be transmitted into consecutive registers, starting from the indicated register address in ADDR[7:0]. 

An SPI transaction is started by asserting the CS_B pin (high-to-low transition), and ended by deasserting the CS_B pin (low-to-
high transition).

* Data bytes must be transmitted to the slave (FXOS8700CQ) using the MOSI pin by the master when R/W = 1. Data bytes will be transmitted 
by the slave (FXOS8700CQ) to the master using the MISO pin when R/W = 0. The first two bytes are always transmitted by the master using the 
MOSI pin. That is, a transaction is always initiated by master. 1

The registers embedded inside FXOS8700CQ are accessed through either an I

2

C, or a SPI serial interface. To enable either 

interface the VDDIO line must be connected to the interface supply voltage. If VDD is not present and VDDIO is present 
FXOS8700CQ is in shutdown mode and communications on the interface are ignored. If VDDIO is held high, VDD can be 
powered off and the communications pins will be in a high impedance state. This will allow communications to continue on the 
bus with other devices.

2

FXOS8700CQ employs an interface mode, auto-detection circuit that will select either I

2

C or SPI interface mode based on the 

state of the SA0 pin during power up or when exiting reset. Once set for I

2

C or SPI operation, the device will remain in I

2

C or SPI 

mode until the device is reset or powered down and the auto-detection process is repeated. Please note that when SPI interface 
mode is desired, care must be taken to ensure that no other slave device drives the common SA0/MISO pin during the 1 ms 
period after a hard or soft reset or powerup event. 

FXOS8700CQ does not have any specific power supply sequencing requirements between VDD and VDDIO voltage supplies to 
ensure normal operation. To ensure correct operation of the I

2

C/SPI auto-detection function, VDDIO should be applied before or 

at the same time as VDD. If this order cannot be maintained, the user should either toggle the RST line or power cycle the VDD 
rail in order to force the auto-detect function to restart and correctly identify the desired interface. FXOS8700CQ will indicate 
completion of the reset sequence by toggling the INT1 pin from logic high to low to high over a 500 ns period. If the INT1 pin was 
already low prior to the reset event, it will only go high.

R/W bit followed by ADDR [6:0] ADDR[7] followed by 7 “don’t care” bits

Data0*

Data1

—

Datan

VDDIO

Digital interface power

SA1/CS_B

I

2

C second least significant bit of device address/SPI chip select

SCL/SCLK

I

2

C/SPI serial clock

SDA/MOSI

I

2

C serial data/SPI master serial data out slave serial data in

SA0/MISO

I

2

C least significant bit of the device address/SPI master serial data in slave out

2

GND

I

2

C

 VDDIO

I

2

C

Floating

SPI