Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

Sensors

40

Freescale Semiconductor, Inc.

The active bit selects between Standby mode and Active mode. The default value is 0 (Standby mode) on reset.

The lnoise bit selects between normal full dynamic range mode and a high sensitivity, low-noise mode. In low-noise mode the 
maximum signal that can be measured is ±4 g. Note: Any thresholds set above 4 g will not be reached.

The f_read bit selects between normal and fast-read modes where the auto-increment counter will also skip over the LSB data 
bytes when f_read = 1. In hybrid mode and with M_CTRL_REG2[hyb_autoinc_mode] = 1, all of the sensor data MSB's can be 
read out with a single 6-byte burst read starting at the OUT_X_MSB register. 

The f_read bit can only be changed while F_SETUP[f_mode] = 0.

 

 

0

0

0

800.0

1.25

400

2.5

0

0

1

400.0

2.5

200

5

0

1

0

200.0

5

100

10

0

1

1

100.0

10

50

20

1

0

0

50.0

20

25

80

1

0

1

12.5

80

6.25

160

1

1

0

6.25

160

3.125

320

1

1

1

1.5625

640

0.7813

1280

st

rst

—

smods[1:0]

slpe

mods[1:0]

0

0

0

0b00

0

0b00

st

The st bit activates the accelerometer self-test function. When st is set to 1, a change will occur in the device output levels for 
each axis, allowing the host application to check the functionality of the transducer and measurement signal chain.
Self-Test Enable: 
0: Self-Test disabled 
1: Self-Test enabled.

rst

The rst bit is used to initiate a software reset. The reset mechanism can be enabled in both Standby and Active modes. When the 
rst bit is set, the boot mechanism resets all functional block registers and loads the respective internal registers with their default 
values. Refer to 

 for further information and a suggested work-around. After setting the rst bit, the system will 

automatically transition to Standby mode. Therefore, if the system was already in Standby mode, the reboot process will 
immediately begin; else if the system was in Active mode the boot mechanism will automatically transition the system from Active 
mode to Standby mode, only then can the reboot process begin. A system reset can also be initiated by pulsing the external RST 
pin high.
The I

2

C and SPI communication systems are also reset to avoid corrupted data transactions. The host application should allow 

1 ms between issuing a software (setting rst bit) or hardware (pulsing RST pin) reset and attempting communications with the 
device over the I

2

C or SPI interfaces. When the SPI interface mode is desired and multiple devices are present on the bus, make 

sure that the bus is quiet (all slave device MISO pins are high-z) during this 1 ms period to ensure the device does not 
inadvertently enter I

2

C mode. See 

 for further information about the interface mode auto-detection circuit.

At the end of the boot process, the rst bit is hardware cleared. 
0: Device reset disabled 
1: Device reset enabled.

smods[1:0]

Accelerometer Sleep mode OSR mode selection. This setting, along with the CTRL_REG1[aslp_rate] ODR setting determines 
the Sleep mode power and noise for acceleration measurements. 
See 

slpe

(1)

Auto-Sleep mode enable:
0: Auto-Sleep is not enabled
1: Auto-Sleep is enabled.