Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트
FXOS8700CQ
Sensors
38
Freescale Semiconductor, Inc.
10.1.6
INT_SOURCE (0x0C) register
Interrupt source register. The bits that are set (logic ‘1’) indicate which function has asserted its interrupt and conversely bits that
are cleared (logic ‘0’) indicate which function has not asserted its interrupt. Additional interrupt flags for magnetic interrupt events
are located in the M_INT_SRC register (0x5E).
are cleared (logic ‘0’) indicate which function has not asserted its interrupt. Additional interrupt flags for magnetic interrupt events
are located in the M_INT_SRC register (0x5E).
Reading the INT_SOURCE register does not clear any interrupt status bits (except for src_a_vecm, see below); the respective
interrupt flag bits are reset by reading the appropriate source register for the function that generated the interrupt.
interrupt flag bits are reset by reading the appropriate source register for the function that generated the interrupt.
Table 27. INT_SOURCE register
src_aslp
src_fifo
src_trans
src_lndprt
src_pulse
src_ffmt
src_a_vecm
src_drdy
0
0
0
0
0
0
0
0
Table 28. INT_SOURCE bit descriptions
Field
Description
src_aslp
Auto-Sleep/Wake interrupt status bit: logic ‘1’ indicates that an interrupt event that can cause a Wake-to-Sleep or Sleep-
to-Wake system mode transition has occurred and logic ‘0’ indicates that no Wake-to-Sleep or Sleep-to-Wake system
mode transition interrupt event has occurred.
The “Wake-to-Sleep” transition occurs when a period of inactivity that exceeds the user-specified time limit
(ASLP_COUNT) has been detected, thus causing the system to transition to a user-specified low ODR setting.
A “Sleep-to-Wake” transition occurs when the user-specified interrupt event has awakened the system, thus causing the
system to transition to the user-specified higher ODR setting.
Reading the SYSMOD register will clear the src_aslp bit.
to-Wake system mode transition has occurred and logic ‘0’ indicates that no Wake-to-Sleep or Sleep-to-Wake system
mode transition interrupt event has occurred.
The “Wake-to-Sleep” transition occurs when a period of inactivity that exceeds the user-specified time limit
(ASLP_COUNT) has been detected, thus causing the system to transition to a user-specified low ODR setting.
A “Sleep-to-Wake” transition occurs when the user-specified interrupt event has awakened the system, thus causing the
system to transition to the user-specified higher ODR setting.
Reading the SYSMOD register will clear the src_aslp bit.
src_fifo
FIFO interrupt status bit: logic ‘1’ indicates that a FIFO interrupt event such as an overflow or watermark (F_STATUS[f_cnt]
= F_STATUS[f_wmrk]) event has occurred and logic ‘0’ indicates that no FIFO interrupt event has occurred.
This bit is cleared by reading the F_STATUS register.
= F_STATUS[f_wmrk]) event has occurred and logic ‘0’ indicates that no FIFO interrupt event has occurred.
This bit is cleared by reading the F_STATUS register.
src_trans
Transient interrupt status bit: logic ‘1’ indicates that an acceleration transient value greater than user-specified threshold
has occurred. and logic ‘0’ indicates that no transient event has occurred.
This bit is asserted whenever TRANSIENT_SRC[ea] is asserted and the functional block interrupt has been enabled.
This bit is cleared by reading the TRANSIENT_SRC register.
has occurred. and logic ‘0’ indicates that no transient event has occurred.
This bit is asserted whenever TRANSIENT_SRC[ea] is asserted and the functional block interrupt has been enabled.
This bit is cleared by reading the TRANSIENT_SRC register.
src_lndprt
Landscape/Portrait orientation interrupt status bit: logic ‘1’ indicates that an interrupt was generated due to a change in the
device orientation status and logic ‘0’ indicates that no change in orientation status was detected.
This bit is asserted whenever PL_STATUS[newlp] is asserted and the functional block interrupt has been enabled.
This bit is cleared by reading the PL_STATUS register.
device orientation status and logic ‘0’ indicates that no change in orientation status was detected.
This bit is asserted whenever PL_STATUS[newlp] is asserted and the functional block interrupt has been enabled.
This bit is cleared by reading the PL_STATUS register.
src_pulse
Pulse interrupt status bit: logic ‘1’ indicates that an interrupt was generated due to single- and/or double- pulse event and
logic ‘0’ indicates that no pulse event was detected.
This bit is asserted whenever PULSE_SRC[ea] is asserted and the functional block interrupt has been enabled.
This bit is cleared by reading the PULSE_SRC register.
logic ‘0’ indicates that no pulse event was detected.
This bit is asserted whenever PULSE_SRC[ea] is asserted and the functional block interrupt has been enabled.
This bit is cleared by reading the PULSE_SRC register.
src_ffmt
Freefall/motion interrupt status bit: logic ‘1’ indicates that the freefall/motion function interrupt is active and logic ‘0’
indicates that no freefall or motion event was detected.
This bit is asserted whenever A_FFMT_SRC[ea] is asserted and the functional block interrupt has been enabled.
This bit is cleared by reading the A_FFMT_SRC register.
indicates that no freefall or motion event was detected.
This bit is asserted whenever A_FFMT_SRC[ea] is asserted and the functional block interrupt has been enabled.
This bit is cleared by reading the A_FFMT_SRC register.
src_a_vecm
Accelerometer vector-magnitude interrupt status bit: logic ‘1’ indicates that an interrupt was generated due to acceleration
vector-magnitude function and logic ‘0’ indicates that no interrupt has been generated. This bit is cleared by reading this
register (INT_SOURCE).
vector-magnitude function and logic ‘0’ indicates that no interrupt has been generated. This bit is cleared by reading this
register (INT_SOURCE).
src_drdy
Data-ready interrupt status bit. In acceleration only mode this bit indicates that new accelerometer data is available to read.
In magnetometer only mode, src_drdy indicates that new magnetic data is available to be read.In hybrid mode, this bit
signals that new acceleration and/or magnetic data is available.
The src_drdy interrupt flag is cleared by reading out the acceleration data in accelerometer only mode and by reading out
the magnetic data in magnetometer only or hybrid modes. In hybrid mode and with M_CTRL_REG2[hyb_autoinc_mode]
= 1, all of the sensor data can be read out in a 12-byte burst read starting at register 0x01 (OUT_X_MSB).
In magnetometer only mode, src_drdy indicates that new magnetic data is available to be read.In hybrid mode, this bit
signals that new acceleration and/or magnetic data is available.
The src_drdy interrupt flag is cleared by reading out the acceleration data in accelerometer only mode and by reading out
the magnetic data in magnetometer only or hybrid modes. In hybrid mode and with M_CTRL_REG2[hyb_autoinc_mode]
= 1, all of the sensor data can be read out in a 12-byte burst read starting at register 0x01 (OUT_X_MSB).