Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

다운로드
페이지 100
FXOS8700CQ
Sensors
Freescale Semiconductor, Inc.
43
10.1.11
CTRL_REG4 [Interrupt Enable Register] (0x2D) register
 
The corresponding functional block interrupt enable bit allows the functional block to route its event detection flag to the system’s 
interrupt controller. The interrupt controller routes the enabled interrupt signals to either the INT1 or INT2 pins depending on the 
settings made in CTRL_REG5.Please note that the interrupt enable bits for the magnetic threshold and vector-magnitude 
interrupts are located in registers 0x52 (MAG_THS_CFG), and 0x69 (M_VECM_CFG), respectively. 
Table 40. CTRL_REG4 register
int_en_aslp
int_en_fifo
int_en_trans
int_en_lndprt
 int_en_pulse
int_en_ffmt
 int_en_a_vecm
 int_en_drdy
0
0
0
0
0
0
0
0
Table 41.   Interrupt Enable Register bit descriptions
Field
Description
int_en_aslp
Sleep interrupt enable
0: Auto-Sleep/Wake interrupt disabled
1‘b1: Auto-Sleep/Wake interrupt enabled
int_en_fifo
FIFO interrupt enable
0: FIFO interrupt disabled
1: FIFO interrupt enabled
int_en_trans
Transient interrupt enable
0: Transient interrupt disabled
1: Transient interrupt enabled
int_en_lndprt
Orientation interrupt enable
0: Orientation (Landscape/Portrait) interrupt disabled
1: Orientation (Landscape/Portrait) interrupt enabled
int_en_pulse
Pulse interrupt enable
0: Pulse detection interrupt disabled
1: Pulse detection interrupt enabled
int_en_ffmt
Freefall/motion interrupt enable
0: Freefall/motion interrupt disabled
1: Freefall/motion interrupt enabled
int_en_a_vecm
Acceleration vector-magnitude interrupt enable
0: Acceleration vector-magnitude interrupt disabled
1: Acceleration vector-magnitude interrupt enabled
int_en_drdy
Data-ready interrupt enable
0: Data-ready interrupt disabled
1: Data-ready interrupt enabled