Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

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FXOS8700CQ
Sensors
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Freescale Semiconductor, Inc.
10.8.2
PL_CFG (0x11) register
This register enables the Portrait/Landscape function and sets the behavior of the debounce counter.
 
 
10.8.3
PL_COUNT (0x12) register
This register sets the debounce count for the orientation state transition. The minimum debounce latency is determined by the 
system ODR value and the value of the PL_COUNT register. Any change to the system ODR or a transition from Active-to-
Standby (or vice-versa) resets the internal landscape/portrait internal debounce counters. When the device is operated in hybrid 
mode, the effective ODR will be half of what is selected by the user, which will also affect the debounce time. For example, if an 
ODR of 400 Hz is selected and the part is also in hybrid mode, the effective ODR is 200 Hz, and the effective debounce time step 
is 5 ms instead of 2.5 ms.
 
 
Table 65. PL_CFG register
dbcntm
pl_en
1
0
0
0
0
0
0
0
Table 66. PL_CFG bit descriptions
Field
Description
dbcntm
Debounce counter mode selection. 
0: Decrements debounce whenever condition of interest is no longer valid.
1: Clears counter whenever condition of interest is no longer valid.
pl_en
Portrait/Landscape detection enable.
0: Portrait/Landscape detection is disabled.
1: Portrait/Landscape detection is enabled.
Table 67. PL_COUNT register
dbnce[7:0]
0b0000_0000
Table 68. PL_Count Relationship with the ODR
ODR (Hz)
Max time range (s)
Time step (ms)
Normal
LPLN
High 
resolution
Low power
Normal
LPLN
High 
resolution
Low power
800
0.319
0.319
0.319
0.319
1.25
1.25
1.25
1.25
400
0.638
0.638
0.638
0.638
2.5
2.5
2.5
2.5
200
1.28
1.28
0.638
1.28
5
5
2.5
5
100
2.55
2.55
0.638
2.55
10
10
2.5
10
50
5.1
5.1
0.638
5.1
20
20
2.5
20
12.5
5.1
20.4
0.638
20.4
20
80
2.5
80
6.25
5.1
20.4
0.638
40.8
20
80
2.5
160
1.56
5.1
20.4
0.638
40.8
20
80
2.5
160