Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

Sensors

8

Freescale Semiconductor, Inc.

 

Device power is supplied through the VDD pin. Power supply decoupling capacitors (100 nF ceramic plus 4.7 

μF bulk) should be 

placed as close as possible to pin 14 of the device. The digital interface supply voltage (VDDIO) should be decoupled with a 
100 nF ceramic capacitor placed as close as possible to pin 1 of the device. 

1

VDDIO

Interface supply voltage

2

BYP

Internal regulator output bypass capacitor connection

3

Reserved

Test reserved, connect to GND

4

SCL/SCLK

I

2

C Serial Clock/SPI Clock

(1)

1. Refer to 

 regarding point-to-point SPI operation.

5

GND

Ground

6

SDA/MOSI

I

2

C Serial Data/SPI Master Out, Slave In

7

SA0/MISO

I

2

C address selection bit 0/SPI Master In, Slave Out

(1)(2)(3)

2. Refer to 

 regarding SPI bus requirements during 1 ms period following a reset.

3. Refer to 

 for I

2

C address options selectable using the SA0 and SA1 pins. 

8

Crst

Magnetic reset capacitor

9

INT2

Interrupt 2

10

SA1/CS_B

I

2

C address selection bit 1/SPI Chip Select (active low)

11

INT1

Interrupt 1

12

GND

Ground

13

Reserved

Test reserved, connect to GND

14

VDD

Sensor supply voltage

15

N/C

Not connected internally

16

RST

Reset input, active high. Connect to GND if unused

1

VDDIO

6

2

3

4

5

13

12

11

10

9

7

8

16

15

14

BYP

Reserved

SCL/SCLK

GND

Reserved

GND

INT1

SA1/CS_B

INT2

SDA/

MOSI

S

A

0

/M

IS

O

Crst

RST

N/C

VDD