Freescale Semiconductor FRDM-FXS-MULTI 데이터 시트

Sensors
Freescale Semiconductor, Inc.

9

The digital control signals SCL, SDA, SA0, SA1, and RST are not tolerant of voltages exceeding VDDIO + 0.3 V. If VDDIO is 
removed, these pins will clamp any logic signals through their internal ESD protection diodes. The function and timing of the two 
interrupt pins (INT1 and INT2) are user programmable through the I

2

C/SPI interface. The SDA and SCL I

2

C connections are 

open drain and therefore require a pullup resistor as shown in the application diagram in 

. The INT1 and INT2 pins may 

also be configured for open-drain operation. If they are configured for open drain, external pullup resistors are required.

 

The QFN package is compliant with the RoHS standards. Please refer to Freescale application note AN4077 for more 
information. 

VDDIO

INT1

INT2

SDA/MOSI

SA0/MISO

RST

VDD

0.1 

μF

0.1 

μF

0.1 

μF

4.7 

μF

SCL/SCLK

SA1/CS_B

VDDIO

VDDIO

VDDIO

VDDIO

(Connect to GND if unused)

Note: Pullup resistors on INT1 and INT2 are not required if these

pins are configured for push/pull (default) operation.

0.1 

μF

Note: Pullup resistors on SCL/SCLK and SDA/MOSI are not 

required if the device is operated in SPI Interface mode.

1

6

2

3

4

5

13

12

11

10

9

7

8

16

15

14

BYP

SCL/SCLK

GND

Reserved

GND

SDA

/MO

SI

SA

0/

MISO

Crst

RST

N/

C

VDD

Reserved

VDDIO

INT1

INT2