Analog Devices AD9211 Evaluation Board AD9211-200EBZ AD9211-200EBZ 데이터 시트

 

Rev. 0 | Page 8 of 28 

ELECTRICAL  

AVDD to AGND 

−0.3 V to +2.0 V 

DRVDD to DRGND 

−0.3 V to +2.0 V 

AGND to DRGND 

−0.3 V to +0.3 V 

AVDD to DRVDD 

−2.0 V to +2.0 V 

D0+/D0− through D9+/D9−  

to DRGND 

−0.3 V to DRVDD + 0.3 V 

DCO to DRGND 

−0.3 V to DRVDD + 0.3 V 

OR to DGND 

−0.3 V to DRVDD + 0.3 V 

CLK+ to AGND 

−0.3 V to +3.9 V 

CLK− to AGND 

−0.3 V to +3.9 V 

VIN+ to AGND  

−0.3 V to AVDD + 0.2 V 

VIN− to AGND 

−0.3 V to AVDD + 0.2 V 

SDIO/DCS to DGND 

−0.3 V to DRVDD + 0.3 V 

PWDN to AGND 

−0.3 V to +3.9 V 

CSB to AGND  

−0.3 V to +3.9 V 

SCLK/DFS to AGND  

−0.3 V to +3.9 V 

ENVIRONMENTAL  

Storage Temperature Range 

−65°C to +125°C 

Operating Temperature Range 

−40°C to +85°C 

Lead Temperature  

(Soldering 10 sec) 

300°C 

Junction Temperature 

150°C 

Stresses above those listed under Absolute Maximum Ratings 
may cause permanent damage to the device. This is a stress 
rating only; functional operation of the device at these or any 
other conditions above those indicated in the operational 
section of this specification is not implied. Exposure to absolute 
maximum rating conditions for extended periods may affect 
device reliability. 

The exposed paddle must be soldered to the ground plane  
for the LFCSP package. Soldering the exposed paddle to the 
customer board increases the reliability of the solder joints, 
maximizing the thermal capability of the package. 

56-Lead LFCSP (CP-56-2) 

30.4 

2.9 

°C/W 

Typical θ

JA

 and θ

JC

 are specified for a 4-layer board in still air. 

Airflow increases heat dissipation, effectively reducing θ

JA

. In 

addition, metal in direct contact with the package leads from 
metal traces, and through holes, ground, and power planes 
reduces the θ

JA

.