Analog Devices AD9211 Evaluation Board AD9211-200EBZ AD9211-200EBZ 데이터 시트
제품 코드
AD9211-200EBZ
AD9211
Rev. 0 | Page 9 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DNC = DO NOT CONNECT
PIN 1
INDICATOR
1
D1–
2
D1+
3
D2–
4
D2+
5
D3–
6
D3+
7
DRVDD
8
DRGND
9
D4–
10
D4+
11
D5–
12
D5+
13
D6–
14
D6+
35 VIN+
36 VIN–
37 AVDD
38 AVDD
39 AVDD
40 CML
41 AVDD
42 AVDD
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
15
D
7–
16
D
7+
17
D
8–
19
(
M
S
B
)
D
9–
21
O
R
–
20
(M
S
B
)
D
9+
22
O
R
+
23
D
R
G
N
D
24
D
R
V
D
D
25
S
D
IO
/D
C
S
26
S
C
L
K
/D
F
S
27
C
S
B
28
R
E
S
E
T
18
D
8+
45
C
L
K
–
46
A
V
D
D
47
D
R
V
D
D
48
D
R
G
N
D
49
D
C
O
–
50
D
C
O
+
51
D
N
C
52
D
N
C
53
D
N
C
54
D
N
C
44
C
L
K
+
43
A
V
D
D
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
AD9211
55
D
0–
(
L
S
B
)
56
D
0+
(
L
S
B
)
06
04
1
-00
4
Figure 4. AD9211 Single Data Rate Mode Pin Configuration
Table 7. Single Data Rate Mode Pin Function Descriptions
Pin No.
Mnemonic
Description
30, 32 to 34, 37 to 39,
41 to 43, 46
41 to 43, 46
AVDD
1.8 V Analog Supply.
7, 24, 47
DRVDD
1.8 V Digital Output Supply.
0 AGND
Analog Ground.
8, 23, 48
Digital Output Ground.
35
VIN+
Analog Input—True.
36
VIN−
Analog Input—Complement.
40 CML
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
optimized internal bias voltage for VIN+/VIN−.
44
CLK+
Clock Input—True.
45
CLK−
Clock Input—Complement.
31
RBIAS
Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V.
28
RESET
CMOS-Compatible Chip Reset (Active Low).
25 SDIO/DCS
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode).
(External Pin Mode).
26
SCLK/DFS
Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
27
CSB
Serial Port Chip Select (Active Low).
29 PWDN
Chip
Power-Down.
49
DCO−
Data Clock Output—Complement.
50
DCO+
Data Clock Output—True.
51 to 54
DNC
Do Not Connect.
55
D0−
D0 Complement Output Bit (LSB).
56
D0+
D0 True Output Bit (LSB).
1
D1−
D1 Complement Output Bit.
2
D1+
D1 True Output Bit.
3
D2−
D2 Complement Output Bit.
4
D2+
D2 True Output Bit.
5
D3−
D3 Complement Output Bit.
6
D3+
D3 True Output Bit.
9
D4−
D4 Complement Output Bit.
10
D4+
D4 True Output Bit.