Analog Devices AD9253 Evaluation Board AD9253-125EBZ AD9253-125EBZ 데이터 시트
제품 코드
AD9253-125EBZ
AD9253
Data Sheet
Rev. 0 | Page 38 of 40
Table 19. Input Clock Phase Adjust Options
Input Clock Phase
Adjust, Bits[6:4]
Adjust, Bits[6:4]
Number of Input Clock Cycles of
Phase Delay
Phase Delay
000 (Default)
0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
010 2
011 3
100 4
101 5
110 6
111 7
Bits[3:0]—Output Clock Phase Adjust
Table 20. Output Clock Phase Adjust Options
Output Clock (DCO),
Phase Adjust, Bits[3:0]
Phase Adjust, Bits[3:0]
DCO Phase Adjustment (Degrees
Relative to D0±x/D1±x Edge)
Relative to D0±x/D1±x Edge)
0000 0
0001 60
0010 120
0011 (Default)
0001 60
0010 120
0011 (Default)
180
0100 240
0101 300
0110 360
0111 420
1000 480
1001 540
1010 600
1011 660
0101 300
0110 360
0111 420
1000 480
1001 540
1010 600
1011 660
Serial Output Data Control (Register 0x21)
The serial output data control register is used to program the
in various output data modes depending upon the data
.
Resolution/Sample Rate Override (Register 0x100)
This register is designed to allow the user to downgrade the device.
Any attempt to upgrade the default speed grade results in a chip
power-down. Settings in this register are not initialized until Bit 0
of the transfer register (Register 0xFF) is written high.
Any attempt to upgrade the default speed grade results in a chip
power-down. Settings in this register are not initialized until Bit 0
of the transfer register (Register 0xFF) is written high.
User I/O Control 2 (Register 0x101)
Bits[7:1]—Open
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM
generator. This feature is used when applying an external
reference.
generator. This feature is used when applying an external
reference.
Bits[2:0]—Open
Table 21. SPI Register Options
Serialization Options Selected
Register 0x21
Contents
Contents
Serial Output Number
of Bits (SONB)
of Bits (SONB)
Frame Mode
Serial Data Mode
DCO Multiplier
Timing Diagram
0x30
16-bit
1×
DDR two-lane bytewise
4 × f
S
Figure 2 (default setting)
0x20
16-bit
1×
DDR two-lane bitwise
4 × f
S
0x10
16-bit
1×
SDR two-lane bytewise
8 × f
S
0x00
16-bit
1×
SDR two-lane bitwise
8 × f
S
0x34
16-bit
2×
DDR two-lane bytewise
4 × f
S
0x24
16-bit
2×
DDR two-lane bitwise
4 × f
S
0x14
16-bit
2×
SDR two-lane bytewise
8 × f
S
0x04
16-bit
2×
SDR two-lane bitwise
8 × f
S
0x40
16-bit
1×
DDR one-lane
8 × f
S
0x32
12-bit
1×
DDR two-lane bytewise
3 × f
S
0x22
12-bit
1×
DDR two-lane bitwise
3 × f
S
0x12
12-bit
1×
SDR two-lane bytewise
6 × f
S
0x02
12-bit
1×
SDR two-lane bitwise
6 × f
S
0x36
12-bit
2×
DDR two-lane bytewise
3 × f
S
0x26
12-bit
2×
DDR two-lane bitwise
3 × f
S
0x16
12-bit
2×
SDR two-lane bytewise
6 × f
S
0x06
12-bit
2×
SDR two-lane bitwise
6 × f
S
0x42
12-bit
1×
DDR one-lane
6 × f
S