Analog Devices AD9253 Evaluation Board AD9253-125EBZ AD9253-125EBZ 데이터 시트
제품 코드
AD9253-125EBZ
Data Sheet
AD9253
Rev. 0 | Page 39 of 40
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the
as a system,
it is recommended that the designer become familiar with these
guidelines, which describes the special circuit connections and
layout requirements that are needed for certain pins.
guidelines, which describes the special circuit connections and
layout requirements that are needed for certain pins.
POWER AND GROUND RECOMMENDATIONS
When connecting power to the
, it is recommended
that two separate 1.8 V supplies be used. Use one supply for
analog (AVDD); use a separate supply for the digital outputs
(DRVDD). For both AVDD and DRVDD, several different
decoupling capacitors should be used to cover both high and
low frequencies. Place these capacitors close to the point of
entry at the PCB level and close to the pins of the part, with
minimal trace length.
analog (AVDD); use a separate supply for the digital outputs
(DRVDD). For both AVDD and DRVDD, several different
decoupling capacitors should be used to cover both high and
low frequencies. Place these capacitors close to the point of
entry at the PCB level and close to the pins of the part, with
minimal trace length.
A single PCB ground plane should be sufficient when using the
. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
is easily achieved.
EXPOSED PAD THERMAL HEAT SLUG
RECOMMENDATIONS
RECOMMENDATIONS
It is required that the exposed pad on the underside of the ADC
be connected to analog ground (AGND) to achieve the best
electrical and thermal performance of the
be connected to analog ground (AGND) to achieve the best
electrical and thermal performance of the
. An exposed
continuous copper plane on the PCB should mate to the
exposed pad, Pin 0. The copper plane should have
several vias to achieve the lowest possible resistive thermal path
for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
only guarantees one tie point. See Figure 75 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
only guarantees one tie point. See Figure 75 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the
,
SILKSCREEN PARTITION
PIN 1 INDICATOR
1
0065-
0
80
Figure 75. Typical PCB Layout
VCM
The VCM pin should be decoupled to ground with a 0.1 μF
capacitor.
capacitor.
REFERENCE DECOUPLING
The VREF pin should be externally decoupled to ground with a
low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF
ceramic capacitor.
low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF
ceramic capacitor.
SPI PORT
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
to keep these signals from transitioning at the con-
verter inputs during critical sampling periods.
CROSSTALK PERFORMANCE
is available in a 48-lead LFCSP package with the
input pairs on either corner of the chip. See Figure 9 for the pin
configuration. To maximize the crosstalk performance on the
board, add grounded filled vias in between the adjacent
channels as shown in Figure 76.
configuration. To maximize the crosstalk performance on the
board, add grounded filled vias in between the adjacent
channels as shown in Figure 76.
GROUNDED
FILLED VIAS
FOR ADDED
CROSSTALK
ISOLATION
VIN
CHANNEL B
VIN
CHANNEL C
VIN
CHANNEL A
VIN
CHANNEL D
PIN 1
1
0065-
0
88
Figure 76. Layout Technique to Maximize Crosstalk Performance