STMicroelectronics Evaluation board for STM32L1 series - with STM32L152ZD MCU STM32L152D-EVAL STM32L152D-EVAL 데이터 시트
제품 코드
STM32L152D-EVAL
UM01018
Hardware and layout
Doc ID 18141 Rev 2
13/42
2.13 Comparator
Three I/Os are used to implement a comparator feature as shown in
.
●
Comparator non-inverting input PB4 connected to LDR (R34).
●
Comparator inverting input PB3 connected to potentiometer (RV3) used as variable
threshold input for comparison to luminosity measured on LDR.
threshold input for comparison to luminosity measured on LDR.
●
Comparator non-inverting input PB5 connected to potentiometer (RV3) used as
analogue voltage input for comparison with internal voltage reference (for instance
Band gap) in order to test analogue Wakeup feature of the MCU.
analogue voltage input for comparison with internal voltage reference (for instance
Band gap) in order to test analogue Wakeup feature of the MCU.
Figure 3.
STM32L152-EVAL comparator features
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Table 10.
Comparator and potentiometer related jumpers
Jumper
Description
Setting
JP17
Potentiometer RV3 is connected to ADC input PB12. Used as ADC input when JP17 is set
as shown (default setting).
as shown (default setting).
Potentiometer RV3 used as LDR variable threshold. Input is connected to comparator
inverting input GPCOMP_IN- (PB3) when JP17 is set as shown.
inverting input GPCOMP_IN- (PB3) when JP17 is set as shown.
Potentiometer RV3 is connected to non-inverting input GPCOMP_IN+(PB5).
The comparator inverting input can be connected to ¼ band gap, ½ band gap, band gap or
DAC internally to test MCU wakeup possibility when an external voltage reaches a
programmable threshold when JP17 is set as shown.
The comparator inverting input can be connected to ¼ band gap, ½ band gap, band gap or
DAC internally to test MCU wakeup possibility when an external voltage reaches a
programmable threshold when JP17 is set as shown.
JP10
PB4 is connected to JTAG connector CN9 (TRST) when JP10 is set as shown (default
setting).
setting).
PB4 is connected to LDR when JP10 is set as shown.
PB12
PB3
PB5
PB3
PB5
PB12
PB3
PB5
PB3
PB5
PB12
PB3
PB5
PB3
PB5
3
2
1
3
2
1