Intel E3-1105C AV8062701048800 데이터 시트

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

-

001

103

The following notes apply to 

, 

.

V

CROSS

Crossing Point Voltage

Single Ended

250

550

mV

RT

1,4,5

V

CROSS_DELTA

Variation of V

CROSS

Single Ended

140

mV

RT

1,4,8

V

MAX

Max Output Voltage

Single Ended

1.15

V

RT

1,6

V

MIN

Min Output Voltage

Single Ended

-0.3

V

RT

1,7

DTY_CYC

Duty Cycle

Diff

40

60

%

Avg

2

1.

Measurement taken from single-ended waveform on a component test board.

2.

Measurement taken from differential waveform on a component test board.

3.

Slew rate measured through V

SWING

 voltage range centered about differential zero.

4.

V

CROSS

 is defined as the voltage where Clock = Clock#.

5.

Only applies to the differential rising edge (i.e., Clock rising and Clock# falling).

6.

The max voltage including overshoot.

7.

The min voltage including undershoot.

8.

The total variation of all V

CROSS

 measurements in any particular system. This is a subset of V

CROSS_MIN/MAX

 (V

CROSS

 

absolute) allowed. The intent is to limit V

CROSS

 induced modulation by setting V

CROSS_DELTA

 to be smaller than V

CROSS

 

absolute.

9.

Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75 mV window 

centered on the average cross point where Clock rising meets Clock# falling (See 

Figure 17, “Differential Clock – 

Differential Measurements” on page 121

). The median cross point is used to calculate the voltage thresholds the 

oscilloscope is to use for the edge rate calculations.

1

Unless otherwise noted, all specifications in this table apply to all processor frequencies. Timing specifications only 

depend on the operating frequency of the memory channel and not the maximum rated frequency.

2

When the single ended slew rate of the input Data or Strobe signals, within a byte group, are below 

1.0 V/ns, the T

SU

 and T

HD

 specifications must be increased by a derrating factor. The input single ended slew rate 

is measured DC to AC levels; V

IL_DC

 to V

IH_AC

 for rising edges, and V

IH_DC

 to V

IL_AC

 for falling edges. Use the 

worse case minimum slew rate measured between Data and Strobe, within a byte group, to determine the required 

derrating value. No derrating is required for single ended slew rates equal to or greater than 1.0 V/ns.

3

Edge Placement Accuracy (EPA): The silicon contains digital logic that automatically adjusts the timing relationship 

between the DDR reference clocks and DDR signals. The BIOS initiates a training procedure that will place a given 

signal appropriately within the clock period. The difference in delay between the signal and clock is accurate to 

within ±EPA. This EPA includes jitter, skew, within die variation and several other effects.

4

Data to Strobe read setup and Data from Strobe read hold minimum requirements specified at the processor pad 

are determined with the minimum Read DQS/DQS# delay.

5

C

WL

 (CAS Write Latency) is the delay, in clock cycles, between the rising edge of CK where a write command is 

referenced and the first rising strobe edge where the first byte of write data is present. The C

WL

 value is 

determined by the value of the CL (CAS Latency) setting.

6

The system memory clock outputs are differential (CLK and CLK#), the CLK rising edge is referenced at the 

crossing point where CLK is rising and CLK# is falling.

7

The system memory strobe outputs are differential (DQS and DQS#), the DQS rising edge is referenced at the 

crossing point where DQS is rising and DQS# is falling, and the DQS falling edge is referenced at the crossing point 

where DQS is falling and DQS# is rising.

8

This value specifies the parameter after write levelling, representing the residual error in the controller after 

training, and does not include any effects from the DRAM itself.