Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
3189
23.6.3
Revision ID;Class Code (RID_CC)—Offset 8h
Access Method
Default: 06040000h
10
0b
RW/V
Interrupt Disable (ID):
This disables pin-based INTx# interrupts on enabled hot plug
and power management events. This bit has no effect on MSI operation. When set,
internal INTx# messages will not be generated. When cleared, internal INTx# messages
are generated if there is an interrupt for hot plug or power management and MSI is not
enabled. This bit does not affect interrupt forwarding from devices connected to the root
port. Assert_INTx and Deassert_INTx messages will still be forwarded to the internal
interrupt controllers if this bit is set. For PCI Bus Emulation Mode compatibility, if the
PCIBEM register is set, this register is RO and returns a value of 0 when read, else it is
RW with the functionality described above.
9
0b
RO
Fast Back to Back Enable (FBE):
Reserved per PCI-Express spec.
8
0b
RW
SERR# Enable (SEE):
When set, enables the root port to generate an SERR# message
when PSTS.SSE is set.
7
0b
RO
Wait Cycle Control (WCC):
Reserved per PCI-Express spec.
6
0b
RW
Parity Error Response Enable (PERE):
Indicates that the device is capable of
reporting parity errors as a master on the backbone.
5
0b
RO
VGA Palette Snoop (VGA_PSE):
Reserved per PCI-Express spec.
4
0b
RO
Memory Write and Invalidate Enable (MWIE):
Reserved per PCI-Express spec.
3
0b
RO
Special Cycle Enable (SCE):
Reserved per PCI-Express and PCI bridge spec.
2
0b
RW
Bus Master Enable (BME):
When set, allows the root port to forward Memory and I/O
Read/Write cycles onto the backbone from a PCI-Express device. When this bit is 0b,
Memory and I/O requests received at a Root Port must be handled as Unsupported
Requests (UR). This bit does not affect forwarding of Completions in either the Upstream
or Downstream direction. The forwarding of Requests other than Memory or I/O
requests is not controlled by this bit.
1
0b
RW
Memory Space Enable (MSE):
When set, memory cycles within the range specified by
the memory base and limit registers can be forwarded to the PCI-Express device. When
cleared, these memory cycles are master aborted on the backbone.
0
0b
RW
I/O Space Enable (IOSE):
When set, I/O cycles within the range specified by the I/O
base and limit registers can be forwarded to the PCI-Express device. When cleared,
these cycles are master aborted on the backbone..
Bit
Range
Default &
Access
Description
Type:
PCI Configuration Register
(Size: 32 bits)
RID_CC:
Power Well:
Core
31
28
24
20
16
12
8
4
0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCC
SC
C
PI
RID