Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
3190
Datasheet
23.6.4
Cache Line Size; Primary Latency Timer; Header Type
(CLS_PLT_HTYPE)—Offset Ch
Access Method
Default: 00810000h
23.6.5
Bus Numbers; Secondary Latency Timer (BNUM_SLT)—Offset
18h
Access Method
Bit
Range
Default &
Access
Description
31:24
06h
RO
Base Class Code (BCC):
Indicates the device is a bridge device.
23:16
04h
RO/V
Sub-Class Code (SCC):
The default indicates the device is a PCI-to-PCI bridge.
15:8
00h
RO/V
Programming Interface (PI):
The value reported in this register is a function of the
Decode Control.Subtractive Decode Enable (SDE) register. SDE Value reported in this
register 0: 00h 1: 01h
7:0
00h
RO/V
Revision ID (RID):
Indicates the revision of the bridge.
Type:
PCI Configuration Register
(Size: 32 bits)
CLS_PLT_HTYPE:
Power Well:
Core
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
MFD
HTY
PE
CT
RS
VD_1
LS
Bit
Range
Default &
Access
Description
31:24
00h
RO
Reserved (RSVD):
Reserved
23
1b
RO
Multi-function Device (MFD):
This bit is '1' to indicate a multi-function device.
22:16
01h
RO/V
Header Type (HTYPE):
The default mode identifies the header layout of the
configuration space, which is a PCI-to-PCI bridge.
15:11
00h
RO
Latency Count (CT):
Reserved per PCI-Express spec
10:8
000b
RO
Reserved (RSVD_1):
Reserved
7:0
00h
RW
Line Size (LS):
This is read/write but contains no functionality, per PCI-Express spec
Type:
PCI Configuration Register
(Size: 32 bits)
BNUM_SLT:
Power Well:
Core