Intel E3815 FH8065301567411 데이터 시트

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

3891

Writes to IC_TAR succeed when one of the following conditions are true: 

• DW_apb_i2c is NOT enabled (IC_ENABLE is set to 0) 
•
• OR 
•
• DW_apb_i2c is enabled (IC_ENABLE=1) 
• AND 
• DW_apb_i2c is NOT engaged in any Master (tx, rx) operation (IC_STATUS[5]=0) 
• AND 
• DW_apb_i2c is enabled to operate in Master mode (IC_CON[0]=1) 
• AND 
• There are NO entries in the TX FIFO (IC_STATUS[2]=1) 

Default: 00001055h

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:24, F:2] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1

R

eserv

ed_13_31

IC

_10BIT

ADDR_MASTE

R

SP

E

C

IA

L

GC

_

O

R

_

S

TAR

T

IC

_T

AR

31:13

0b

RW

Reserved.

12

1h

RW

This bit controls whether the DW_apb_i2c starts its 

transfers in 7-or 10-bit addressing mode when acting as a master.

11

0h

RW

This bit indicates whether software performs a General Call or START BYTE 

command. 
•

0 = ignore bit 10 GC_OR_START and use IC_TAR normally 

•

1 = perform special I2C command as specified in GC_OR_START bit 

10

0h

RW

If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a 

General Call(0) or START(1) byte command is to be performed by the DW_apb_i2c.

9:0

55h

RW

This is the target address for any master transaction. When transmitting a 

General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write 

only once into these bits.