Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
3892
Datasheet
26.9.3
I2C Slave Address Register (IC_SAR)—Offset 8h
The IC SAR Address Register holds the slave address when the I2C is operating as a
slave.
Access Method
Default: 00000055h
26.9.4
I2C High Speed Master Mode Code Address Register
(IC_HS_MADDR)—Offset Ch
Note: It is not necessary to perform any write to this register if DW_apb_i2c is enabled
as an I2C slave only.
Access Method
Default: 00000001h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:24, F:2] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1
R
es
er
ve
d
_10
_31
IC
_S
AR
Bit
Range
Default &
Access
Field Name (ID): Description
31:10
0b
RW
Reserved_10_31:
Reserved.
9:0
55h
RW
IC_SAR:
The IC_SAR holds the slave address when the I2C is operating as a slave. For
7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the
I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0.
Writes at other times have no effect.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:24, F:2] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R
eserv
ed
_3_31
IC_H
S_MAR