Intel E3815 FH8065301567411 데이터 시트
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제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4511
34.3.48
RC—Offset 64h
RC - RTC Configuration
Access Method
Default: 00000000h
34.3.49
BCS - BIOS Control Status (BCS)—Offset 6Ch
Access Method
Default: 00000002h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ILB_BASE_ADDRESS Type:
PCI Configuration Register (Size: 32
bits)
ILB_BASE_ADDRESS Reference:
ILB_BASE_ADDRESS Reference:
[B:0, D:31, F:0] + 50h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
0
UL
LL
Bit
Range
Default &
Access
Description
31:2
0b
RO
RSVD0:
Reserved
1
0b
RW/L
UL:
Upper 128 Byte Lock (UL): When set, bytes 38h-3Fh in the upper 128 byte bank of
RTC RAM are locked. Writes will be dropped and reads will not return any guaranteed
data.
0
0b
RW/L
LL:
Lower 128 Byte Lock (LL): When set, bytes 38h-3Fh in the lower 128 byte bank of
RTC RAM are locked. Writes will be dropped and reads will not return any guaranteed
data.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ILB_BASE_ADDRESS Type:
PCI Configuration Register (Size: 32
bits)
ILB_BASE_ADDRESS Reference:
ILB_BASE_ADDRESS Reference:
[B:0, D:31, F:0] + 50h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
RSV
D
0
SMIWP
E
N
SMIW
PS
T
Bit
Range
Default &
Access
Description
31:2
0b
RO
RSVD0:
Reserved
1
1b
RW
SMIWPEN:
SMI WP Enable (SMIWPEN): When this bit is set to a 1, it enables the LPC
to generate SMI upon not SMM code is trying to set BC.WP from a 0 to a 1 while BC.LE
is set.