Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
4512
Datasheet
34.3.50
LE—Offset 70h
Access Method
Default: 00000003h
34.3.51
NMI (GNMI)—Offset 80h
NMI register
Access Method
Default: 00000004h
0
0b
RW/1C
SMIWPST:
SMI WP Status (SMIWPST): Set when SMI is generated upon trying to set
BC.WP from a 0 to a 1 by not SMM code (while BC.LE and SMIWPEN are set). Write a 1
to this bit should clear it and clear the SMI (send DEASSERT_SMI)
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ILB_BASE_ADDRESS Type:
PCI Configuration Register (Size: 32
bits)
ILB_BASE_ADDRESS Reference:
ILB_BASE_ADDRESS Reference:
[B:0, D:31, F:0] + 50h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
R
SVD0
IRQ12C
IRQ1C
Bit
Range
Default &
Access
Description
31:2
0b
RO
RSVD0:
Reserved
1
1b
RW
IRQ12_CAUSE (IRQ12C):
When software sets the bit to 1, IRQ12 will be high
(asserted), When software set bit to 0,IRQ12 will be low (deasserted). default for this
bit is 1
0
1b
RW
IRQ1_CAUSE (IRQ1C):
When software sets the bit to 1, IRQ11 will be high (asserted),
When software set bit to 0,IRQ1 will be low (deasserted). default for this bit is 1
Type:
Memory Mapped I/O Register
(Size: 32 bits)
GNMI:
ILB_BASE_ADDRESS Type:
PCI Configuration Register (Size: 32
bits)
ILB_BASE_ADDRESS Reference:
ILB_BASE_ADDRESS Reference:
[B:0, D:31, F:0] + 50h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
RSV
D
0
NMI2
SMIEN
N
M
I2SMIST
NMIN
NMIN
S
GN
MIED
GNM
IE
GNMI
S