Infineon 1024MB, 800MHz, DDR II, PC6400, CL6 HYS64T128000EU-2.5C2 사용자 설명서
제품 코드
HYS64T128000EU-2.5C2
HYS[64/72]T512020EU–[25F/2.5/3S]–A
Unbuffered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.0, 2008-06
17
06112008-YHWK-B105
3.3
Speed Grade Definitions
TABLE 12
Speed Grade Definition
TABLE 13
Speed Grade Definition
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
Speed Grade
DDR2–800D
DDR2–800E
Unit
Note
QAG Sort Name
–25F
–2.5
CAS-RCD-RP latencies
5–5–5
6–6–6
t
CK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
Clock Period
@ CL = 3
t
CK
5
8
5
8
ns
@ CL = 4
t
CK
3.75
8
3.75
8
ns
@ CL = 5
t
CK
2.5
8
3
8
ns
@ CL = 6
t
CK
2.5
8
2.5
8
ns
Row Active Time
t
RAS
45
70k
45
70k
ns
Row Cycle Time
t
RC
57.5
—
60
—
ns
RAS-CAS-Delay
t
RCD
12.5
—
15
—
ns
Row Precharge Time
t
RP
12.5
—
15
—
ns
Speed Grade
DDR2–667D
Unit
Note
QAG Sort Name
–3S
CAS-RCD-RP latencies
5–5–5
t
CK
Parameter
Symbol
Min.
Max.
—
Clock Period
@ CL = 3
t
CK
5
8
ns
@ CL = 4
t
CK
3.75
8
ns
@ CL = 5
t
CK
3
8
ns
Row Active Time
t
RAS
45
70k
ns
Row Cycle Time
t
RC
60
—
ns
RAS-CAS-Delay
t
RCD
15
—
ns
Row Precharge Time
t
RP
15
—
ns