Infineon 1024MB, 800MHz, DDR II, PC6400, CL6 HYS64T128000EU-2.5C2 사용자 설명서
제품 코드
HYS64T128000EU-2.5C2
HYS[64/72]T512020EU–[25F/2.5/3S]–A
Unbuffered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.0, 2008-06
25
06112008-YHWK-B105
TABLE 17
Definitions for
I
DD
Self-Refresh Current
CKE
CKE
≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING.
I
DD6
current values are guaranteed up to
T
CASE
of 85
°C max.
I
DD6
All Bank Interleave Read Current
All banks are being interleaved at minimum
All banks are being interleaved at minimum
t
RC
without violating
t
RRD
using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS.
I
out
= 0 mA.
I
DD7
1)
V
DDQ
= 1.8 V
± 0.1 V;
V
DD
= 1.8 V
± 0.1 V
2)
I
DD
specifications are tested after the device is properly initialized and
I
DD
parameter are specified with ODT disabled.
3) Definitions for
I
DD
see
4) For two rank modules: All active current measurements in the same
I
DD
current mode. The other rank is in
I
DD2P
Precharge Power-Down
Mode.
5) For details and notes see the relevant Qimonda component data sheet.
6)
6)
I
DD1
,
I
DD4R
and
I
DD7
current measurements are defined with the outputs disabled (
I
OUT
= 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
Parameter
Description
LOW
V
IN
≤
V
IL(ac).MAX
, HIGH is defined as
V
IN
≥
V
IH(ac).MIN
STABLE
Inputs are stable at a HIGH or LOW level.
FLOATING
Inputs are
V
REF
=
V
DDQ
/2
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
Parameter
Symbol Note
1)2)
3)4)5)