AMD Typewriter x86 사용자 설명서

22007E/0—November 1999

The instruction control unit (ICU) is the control center for the
AMD Athlon processor. The ICU controls the following
resources—the centralized in-flight reorder buffer, the integer
scheduler, and the floating-point scheduler. In turn, the ICU is
responsible for the following functions — MacroOP dispatch,
MacroOP retirement, register and flag dependency resolution
and renaming, execution resource management, interrupts,
exceptions, and branch mispredictions.

The ICU takes the three MacroOPs per cycle from the early
decoders and places them in a centralized, fixed-issue reorder
buffer. This buffer is organized into 24 lines of three MacroOPs
each. The reorder buffer allows the ICU to track and monitor up
to 72 in-flight MacroOPs (whether integer or floating-point) for
maximum instruction throughput. The ICU can simultaneously
dispatch multiple MacroOPs from the reorder buffer to both the
integer and floating-point schedulers for final decode, issue,
and execution as OPs. In addition, the ICU handles exceptions
and manages the retirement of MacroOPs.

T h e   L 1   d a t a   c a c h e   c o n t a i n s   t w o   6 4 -b i t   p o r t s .   I t   i s   a
w r i t e -a l l o c a t e   a n d   w r i t eb a ck   c a ch e   th a t   u s e s   a n   L RU
replacement policy. The data cache and instruction cache are
both two-way set-associative and 64-Kbytes in size. It is divided
into 8 banks where each bank is 8 bytes wide. In addition, this
cache supports the MOESI (Modified, Owner, Exclusive,
Shared, and Invalid) cache coherency protocol and data parity.

The L1 data cache has an associated two-level TLB structure.
The first-level TLB is fully associative and contains 32 entries
(24 that map 4-Kbyte pages and eight that map 2-Mbyte or
4 -M by t e   p a g e s ) .   Th e   s e c o n d -l eve l   T L B   i s   fo u r -way   s e t
associative and contains 256 entries, which can map 4-Kbyte
pages.