AMD Typewriter x86 사용자 설명서
AMD Athlon™ Processor Microarchitecture
135
22007E/0—November 1999
AMD Athlon™ Processor x86 Code Optimization
Integer Scheduler
The integer scheduler is based on a three-wide queuing system
(also known as a reservation station) that feeds three integer
execution positions or pipes. The reservation stations are six
en tr ies deep, fo r a total queuing system of 18 integer
MacroOPs.Each reservation station divides the MacroOPs into
integer and address generation OPs, as required.
(also known as a reservation station) that feeds three integer
execution positions or pipes. The reservation stations are six
en tr ies deep, fo r a total queuing system of 18 integer
MacroOPs.Each reservation station divides the MacroOPs into
integer and address generation OPs, as required.
Integer Execution Unit
The integer execution pipeline consists of three identical
pipes — 0, 1, and 2. Each integer pipe consists of an integer
execution unit (IEU) and an address generation unit (AGU).
The integer execution pipeline is organized to match the three
MacroOP dispatch pipes in the ICU as shown in Figure 2 on
page 1 35 . MacroO Ps are broke n dow n into OP s in the
schedulers. OPs issue when their operands are available either
from the register file or result buses.
pipes — 0, 1, and 2. Each integer pipe consists of an integer
execution unit (IEU) and an address generation unit (AGU).
The integer execution pipeline is organized to match the three
MacroOP dispatch pipes in the ICU as shown in Figure 2 on
page 1 35 . MacroO Ps are broke n dow n into OP s in the
schedulers. OPs issue when their operands are available either
from the register file or result buses.
OPs are executed when their operands are available. OPs from
a single MacroOP can execute out-of-order. In addition, a
particular integer pipe can be executing two OPs from different
MacroOPs (one in the IEU and one in the AGU) at the same
time.
a single MacroOP can execute out-of-order. In addition, a
particular integer pipe can be executing two OPs from different
MacroOPs (one in the IEU and one in the AGU) at the same
time.
Figure 2. Integer Execution Pipeline
IE U 1
IE U 1
I n s t r u c t i o n C o n t r o l U n it a n d R e g i s t e r F ile s
In t e g e r M u lt ip ly ( IM U L )
In t e g e r M u lt ip ly ( IM U L )
IE U 0
IE U 0
A G U 0
A G U 0
A G U 1
A G U 1
IE U 2
IE U 2
A G U 2
A G U 2
M a c r o O P s
M a c r o O P s
P ip e l in e
P i p e li n e
S t a g e
S t a g e
In t e g e r S c h e d u le r
( 1 8 - e n t r y )
7
7
8
8