AMD Typewriter x86 사용자 설명서
138
AMD Athlon™ Processor Microarchitecture
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
Load-Store Unit (LSU)
The load-store unit (LSU) manages data load and store accesses
to the L1 data cache and, if required, to the backside L2 cache
or system memory. The 44-entry LSU provides a data interface
for both the integer scheduler and the floating-point scheduler.
It consists of two queues — a 12-entry queue for L1 cache load
and store accesses and a 32-entry queue for L2 cache or system
memory load and store accesses. The 12-entry queue can
request a maximum of two L1 cache loads and two L1 cache
(32-bits) stores per cycle. The 32-entry queue effectively holds
requests that missed in the L1 cache probe by the 12-entry
queue. Finally, the LSU ensures that the architectural load and
store ordering rules are preserved (a requirement for x86
architecture compatibility).
to the L1 data cache and, if required, to the backside L2 cache
or system memory. The 44-entry LSU provides a data interface
for both the integer scheduler and the floating-point scheduler.
It consists of two queues — a 12-entry queue for L1 cache load
and store accesses and a 32-entry queue for L2 cache or system
memory load and store accesses. The 12-entry queue can
request a maximum of two L1 cache loads and two L1 cache
(32-bits) stores per cycle. The 32-entry queue effectively holds
requests that missed in the L1 cache probe by the 12-entry
queue. Finally, the LSU ensures that the architectural load and
store ordering rules are preserved (a requirement for x86
architecture compatibility).
Figure 4. Load/Store Unit
Data Cache
2-way,
64Kbytes
LSU
44-Entry
Result Buses
from
Core
Operand
Buses
Store Data
to BIU