AMD Typewriter x86 사용자 설명서

22007E/0—November 1999

The floating-point execution unit (FPU) is implemented as a
coprocessor that has its own out-of-order control in addition to
the data path. The FPU handles all register operations for x87
instructions, all 3DNow! operations, and all MMX operations.
The FPU consists of a stack renaming unit, a register renaming
unit, a scheduler, a register file, and three parallel execution
units. Figure 3 shows a block diagram of the dataflow through
the FPU.

As shown in Figure 3 on page 137, the floating-point logic uses
three separate execution positions or pipes for superscalar x87,
3DNow! and MMX operations. The first of the three pipes is
generally known as the adder pipe (FADD), and it contains
3DNow! add, MMX ALU/shifter, and floating-point add
execution units. The second pipe is known as the multiplier
(FMUL). It contains a 3DNow!/MMX multiplier/reciprocal unit,
an MMX ALU and a floating-point multiplier/divider/square
root unit. The third pipe is known as the floating-point
load/store (FSTORE), which handles floating-point constant
loads (FLDZ, FLDPI, etc.), stores, FILDs, as well as many OP
primitives used in VectorPath sequences. 

• MMX™ ALU
• 3DNow!™

• MMX™ ALU
• 3DNow!™

• MMX ALU
• MMX Mul
• 3DNow!

• MMX ALU
• MMX Mul
• 3DNow!