AMD Typewriter x86 사용자 설명서
22007E/0—November 1999
AMD Athlon™ Processor x86 Code Optimization
Introduction
155
Appendix C
Implementation of
Write Combining
Write Combining
Introduction
This appendix describes the memory write-combining feature
as implemented in the AMD Athlon™ processor family. The
AMD Athlon processor supports the memory type and range
register (MTRR) and the page attribute table (PAT) extensions,
which allow software to define ranges of memory as either
writeback (WB), write-protected (WP), writethrough (WT),
uncacheable (UC), or write-combining (WC).
as implemented in the AMD Athlon™ processor family. The
AMD Athlon processor supports the memory type and range
register (MTRR) and the page attribute table (PAT) extensions,
which allow software to define ranges of memory as either
writeback (WB), write-protected (WP), writethrough (WT),
uncacheable (UC), or write-combining (WC).
Defining the memory type for a range of memory as WC or WT
allows the processor to conditionally combine data from
multiple write cycles that are addressed within this range into a
merge buffer. Merging multiple write cycles into a single write
cycle reduces processor bus utilization and processor stalls,
thereby increasing the overall system performance.
allows the processor to conditionally combine data from
multiple write cycles that are addressed within this range into a
merge buffer. Merging multiple write cycles into a single write
cycle reduces processor bus utilization and processor stalls,
thereby increasing the overall system performance.
To understand the information presented in this appendix, the
reader should possess a knowledge of K86™ processors, the x86
architecture, and programming requirements.
reader should possess a knowledge of K86™ processors, the x86
architecture, and programming requirements.