AMD Typewriter x86 사용자 설명서

22007E/0—November 1999

MOVD       [foo], MM1    ;store lower half
PUNPCKHDQ  MM1, MM1      ;get upper half into lower half
MOVD       [foo+4], MM1  ;store lower half
...
ADD        EAX, [foo]    ;fine
ADD        EDX, [foo+4]  ;fine

If the following condition is present, there is a misaligned
store-buffer data forwarding restriction:

■

The store or load address is misaligned. For example, a
quadword store is not aligned to a quadword boundary, a
doubleword store is not aligned to doubleword boundary,
etc.

A common case of misaligned store-data forwarding involves
the passing of misaligned quadword floating-point data on the
doubleword-aligned integer stack. Avoid the type of code shown
in the following example.

MOV 

ESP, 24h

FSTP  QWORD PTR [ESP] ;esp=24
.

;store occurs to quadword

.

; misaligned address

.
FLD 

QWORD PTR[ESP]

;quadword load cannot forward
; from quadword misaligned
; ‘fstp[esp]’ store OP

If the following condition is present, there is a high-byte
store-data buffer forwarding restriction:

■

The store data is from a high-byte register (AH, BH, CH,
DH).

Avoid the type of code shown in the following example.

MOV EAX, 10h
MOV [EAX], BH

;high-byte store

.
MOV DL, [EAX]

;load cannot forward from
; high-byte store