Texas Instruments 28xxx 사용자 설명서
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Counter-Compare Submodule Registers
Table 4-6. Counter-Compare A Register (CMPA) Field Descriptions
Bits
Name
Description
15-0
CMPA
The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When
the values are equal, the counter-compare module generates a "time-base counter equal to counter
compare A" event. This event is sent to the action-qualifier where it is qualified and converted it into one
or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending
on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the
AQCTLA and AQCTLB registers include:
the values are equal, the counter-compare module generates a "time-base counter equal to counter
compare A" event. This event is sent to the action-qualifier where it is qualified and converted it into one
or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending
on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the
AQCTLA and AQCTLB registers include:
•
Do nothing; the event is ignored.
•
Clear: Pull the EPWMxA and/or EPWMxB signal low
•
Set: Pull the EPWMxA and/or EPWMxB signal high
•
Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the CMPCTL[SHDWAMODE] bit. By default this
register is shadowed.
register is shadowed.
•
If CMPCTL[SHDWAMODE] = 0, then the shadow is enabled and any write or read will automatically
go to the shadow register. In this case, the CMPCTL[LOADAMODE] bit field determines which event
will load the active register from the shadow register.
go to the shadow register. In this case, the CMPCTL[LOADAMODE] bit field determines which event
will load the active register from the shadow register.
•
Before a write, the CMPCTL[SHDWAFULL] bit can be read to determine if the shadow register is
currently full.
currently full.
•
If CMPCTL[SHDWAMODE] = 1, then the shadow register is disabled and any write or read will go
directly to the active register, that is the register actively controlling the hardware.
directly to the active register, that is the register actively controlling the hardware.
•
In either mode, the active and shadow registers share the same memory map address.
Figure 4-7. Counter-Compare B Register (CMPB)
15
0
CMPB
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-7. Counter-Compare B Register (CMPB) Field Descriptions
Bits
Name
Description
15-0
CMPB
The value in the active CMPB register is continuously compared to the time-base counter (TBCTR). When
the values are equal, the counter-compare module generates a "time-base counter equal to counter
compare B" event. This event is sent to the action-qualifier where it is qualified and converted it into one
or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending
on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the
AQCTLA and AQCTLB registers include:
the values are equal, the counter-compare module generates a "time-base counter equal to counter
compare B" event. This event is sent to the action-qualifier where it is qualified and converted it into one
or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending
on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the
AQCTLA and AQCTLB registers include:
•
Do nothing. event is ignored.
•
Clear: Pull the EPWMxA and/or EPWMxB signal low
•
Set: Pull the EPWMxA and/or EPWMxB signal high
•
Toggle the EPWMxA and/or EPWMxB signal
Shadowing of this register is enabled and disabled by the CMPCTL[SHDWBMODE] bit. By default this
register is shadowed.
register is shadowed.
•
If CMPCTL[SHDWBMODE] = 0, then the shadow is enabled and any write or read will automatically
go to the shadow register. In this case, the CMPCTL[LOADBMODE] bit field determines which event
will load the active register from the shadow register:
go to the shadow register. In this case, the CMPCTL[LOADBMODE] bit field determines which event
will load the active register from the shadow register:
•
Before a write, the CMPCTL[SHDWBFULL] bit can be read to determine if the shadow register is
currently full.
currently full.
•
If CMPCTL[SHDWBMODE] = 1, then the shadow register is disabled and any write or read will go
directly to the active register, that is the register actively controlling the hardware.
directly to the active register, that is the register actively controlling the hardware.
•
In either mode, the active and shadow registers share the same memory map address.
Registers
98
SPRU791D – November 2004 – Revised October 2007