Texas Instruments TMS320C642x DSP 사용자 설명서
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2.4.1
Refresh Mode
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[12:0]
DDR_BA[2:0]
DDR_DQM[3:0]
RFR
DDR_CLK
Peripheral Architecture
The DDR2 memory controller issues refresh commands to the DDR2 SDRAM memory (
). REFR
is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks
selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a
rate defined by the refresh rate (RR) bit in the SDRAM refresh control register (SDRCR). Page information
is always invalid before and after a REFR command; thus, a refresh cycle always forces a page miss. This
type of refresh cycle is often called autorefresh. Autorefresh commands may not be disabled within the
DDR2 memory controller. See
selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a
rate defined by the refresh rate (RR) bit in the SDRAM refresh control register (SDRCR). Page information
is always invalid before and after a REFR command; thus, a refresh cycle always forces a page miss. This
type of refresh cycle is often called autorefresh. Autorefresh commands may not be disabled within the
DDR2 memory controller. See
for more details on REFR command scheduling.
Figure 4. Refresh Command
SPRUEM4A – November 2007
DDR2 Memory Controller
13