Texas Instruments DAC3484 사용자 설명서
Software Control
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FIFO: allows the configuration of the FIFO and FIFO sync sources.
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LVDS delay: provides internal delay of either the LVDS DATA or LVDS DATACLK to help meet the
input setup/hold time.
input setup/hold time.
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Data Routing: provides flexible routing of the A, B, C, and D sample input data to the appropriate
digital path.
Note: the DAC3482 does not support this mode
digital path.
Note: the DAC3482 does not support this mode
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SIF Control: provides control of the Serial Interface (3-wires or 4-wires) and Serial Interface Sync (SIF
Sync).
Sync).
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Input Format: provides control of the input data format (i.e., 2’s complement or offset binary).
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Parity: provides configuration of the parity input.
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PLL Settings: provides configuration of the on-chip PLL circuitry.
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Temperature Sensor: provides temperature monitoring of DAC3484/2 die temperature.
2.2.1.1
LVDS Delay Settings
The TSW3100 pattern generator sends out LVDS DATA and DATACLK as edge-aligned signal. The
following options can be implemented to meet the minimum setup and hold time of DAC348x data
latching:
following options can be implemented to meet the minimum setup and hold time of DAC348x data
latching:
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Set the on-chip LVDS DATACLOCK delay. Typical setting of 160ps or more will help meet the timing
requirement for most of the TSW3100 + DAC348x EVM setup. This LVDS DATACLOCK delay does
not account for additional PCB trace-to-trace delay variation, only the internal DATACLK delay.
requirement for most of the TSW3100 + DAC348x EVM setup. This LVDS DATACLOCK delay does
not account for additional PCB trace-to-trace delay variation, only the internal DATACLK delay.
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Modify the external LVDS DATACLK PCB trace delay: Additional trace length on the bottom side of the
PCB can be added to the LVDS DATACLK PCB trace length. Set SJP9, SJP10, SJP11, and SJP12 to
2-3 position for approximately 220ps of trace delay.
PCB can be added to the LVDS DATACLK PCB trace length. Set SJP9, SJP10, SJP11, and SJP12 to
2-3 position for approximately 220ps of trace delay.
2.2.1.2
PLL Settings
Figure 3. PLL Configuration
Follow the steps below to configure the PLL.
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Enable PLL
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Uncheck PLL reset and PLL sleep
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Set M and N ratio such that F
DAC
= (M)/(N)×Fref
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Set the prescaler such that the F
DAC
×prescaler is within 3.3GHz and 4.0GHz
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Set VCO Bias Tune to “1”
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Charge Pump setting
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If stability (P×M) is less than 120, then set to “Single
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If stability (P×M) is greater than 120, then set to “Double” or install external loop filter
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Adjust the Freq. Tune (coarse tune) accordingly.
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DAC3484/DAC3482 EVM
SLAU336 – March 2011
© 2011, Texas Instruments Incorporated