Texas Instruments DAC3484 사용자 설명서
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Software Control
2.2.2
Digital Block Options
Figure 4. Digital Block Options
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Interpolation: allows control of the data rate versus DAC sampling rate ratio (i.e. data rate ×
interpolation = DAC sampling rate).
interpolation = DAC sampling rate).
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Digital Mixer: allows control of the coarse mixer function.
Note: If fine mixer (NCO) is used, the “Enable Mixer” button must be checked, and the coarse
mixer must be bypassed. See NCO section for detail.
Note: If fine mixer (NCO) is used, the “Enable Mixer” button must be checked, and the coarse
mixer must be bypassed. See NCO section for detail.
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Inverse sinx/x filter: allows compensation of the sinx/x attenuation of the DAC output.
Note: If inverse sinx/x filter is used, the input data digital full-scale must be backed off accordingly
to avoid digital saturation.
Note: If inverse sinx/x filter is used, the input data digital full-scale must be backed off accordingly
to avoid digital saturation.
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Clock Receiver Sleep: allows the DAC clock receiver to be in sleep mode. The DAC has minimum
power consumption in this mode.
power consumption in this mode.
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Clock Divider Sync: allows the syncing of the internal divided-down clocks using either Frame,
Sync, or OSTR signal. Enable the divider sync as part of the initialization procedure or
resynchronization procedure.
Sync, or OSTR signal. Enable the divider sync as part of the initialization procedure or
resynchronization procedure.
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Group Delay: allows adjustment of group delay for each I/Q channel. This is useful for wideband
sideband suppression.
sideband suppression.
●
Offset Adjustment: allows adjustment of DC offset to minimize the LO feed-through of the modulator
output. This section requires sync for proper operation. The sync options are listed below:
output. This section requires sync for proper operation. The sync options are listed below:
O REGWR: auto-sync from SIF register write.
O OSTR: sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with
OSTR set as sync source
O SYNC: sync from the external LVDS SYNC signal.
O SIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync event.
●
QMC Adjustment: allows adjustment of the gain and phase of the I/Q channel to minimize sideband
power of the modulator output.
power of the modulator output.
O REGWR: auto-sync from SIF register write.
O OSTR: sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with
OSTR set as sync source
O SYNC: sync from the external LVDS SYNC signal.
O SIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync event.
5
SLAU336 – March 2011
DAC3484/DAC3482 EVM
© 2011, Texas Instruments Incorporated