Intel Pentium D 940 사용자 매뉴얼

차례

• Contents Contents

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  • Figures

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  • Tables

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• Revision History Revision History

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• Intel® Pentium® D Processor 900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 Features

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• Intel® Pentium® D Processor 900D Sequence and Intel® Pentium® Processor Extreme Edition 955D, 965D

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• 1 Introduction

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  • 1.1 Terminology

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    • 1.1.1 Processor Packaging Terminology

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  • 1.2 References

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    • Table 1. References

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• 2 Electrical Specifications

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  • 2.1 Power and Ground Lands

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  • 2.2 Decoupling Guidelines

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    • 2.2.1 VCC Decoupling

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    • 2.2.2 VTT Decoupling

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    • 2.2.3 FSB Decoupling

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  • 2.3 Voltage Identification

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    • Table 2. Voltage Identification Definition

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  • 2.4 Reserved, Unused, and TESTHI Signals

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  • 2.5 Voltage and Current Specification

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    • 2.5.1 Absolute Maximum and Minimum Ratings

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      • Table 3. Absolute Maximum and Minimum Ratings

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    • 2.5.2 DC Voltage and Current Specification

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      • Table 4. Voltage and Current Specifications

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      • Table 5. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and 775_VR_CONFIG_05B (Performance) Processors

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      • Figure 1. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and 775_VR_CONFIG_05B (Performance) Processors

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    • 2.5.3 VCC Overshoot

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      • Table 6. VCC Overshoot Specifications1,2

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      • Figure 2. VCC Overshoot Example Waveform

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    • 2.5.4 Die Voltage Validation

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  • 2.6 Signaling Specifications

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    • 2.6.1 FSB Signal Groups

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      • Table 7. FSB Signal Groups (Sheet 2 of 2)

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      • Table 8. Signal Characteristics

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      • Table 9. Signal Reference Voltages

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    • 2.6.2 GTL+ Asynchronous Signals

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    • 2.6.3 Processor DC Specifications

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      • Table 10. GTL+ Signal Group DC Specifications

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      • Table 11. GTL+ Asynchronous Signal Group DC Specifications

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      • Table 12. TAP Signal Group DC Specifications

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      • Table 13. VTTPWRGD DC Specifications

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      • Table 14. BSEL[2:0] and VID[5:0] DC Specifications

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      • Table 15. MSID [1,0] and BOOTSELECT DC Specifications

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      • 2.6.3.1 GTL+ Front Side Bus Specifications

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        • Table 16. GTL+ Bus Voltage Definitions

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  • 2.7 Clock Specifications

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    • 2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

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      • Table 17. Core Frequency to FSB Multiplier Configuration

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    • 2.7.2 FSB Frequency Select Signals (BSEL[2:0])

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      • Table 18. BSEL[2:0] Frequency Table for BCLK[1:0]

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    • 2.7.3 Phase Lock Loop (PLL) and Filter

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      • Figure 3. Phase Lock Loop (PLL) Filter Requirements

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    • 2.7.4 BCLK[1:0] Specifications

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      • Table 19. Front Side Bus Differential BCLK Specifications

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• 3 Package Mechanical Specifications

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  • Figure 4. Processor Package Assembly Sketch

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  • 3.1 Package Mechanical Drawing

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    • Figure 5. Processor Package Drawing Sheet 1 of 3

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    • Figure 6. Processor Package Drawing Sheet 2 of 3

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    • Figure 7. Processor Package Drawing Sheet 3 of 3

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  • 3.2 Processor Component Keep-Out Zones

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  • 3.3 Package Loading Specifications

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    • Table 20. Processor Loading Specifications

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  • 3.4 Package Handling Guidelines

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    • Table 21. Package Handling Guidelines

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  • 3.5 Package Insertion Specifications

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  • 3.6 Processor Mass Specification

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  • 3.7 Processor Materials

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    • Table 22. Processor Materials

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  • 3.8 Processor Markings

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    • Figure 8. Processor Top-Side Markings Example (Intel® Pentium® D Processor 900 Sequence)

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    • Figure 9. Processor Top-Side Markings Example (Intel® Pentium® Processor Extreme Edition 955, 965)

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  • 3.9 Processor Land Coordinates

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    • Figure 10. Processor Land Coordinates and Quadrants (Top View)

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• 4 Land Listing and Signal Descriptions

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  • 4.1 Processor Land Assignments

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    • Figure 11. land-out Diagram (Top View - Left Side)

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    • Figure 12. land-out Diagram (Top View - Right Side)

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    • Table 23. Alphabetical Land Assignments

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    • Table 24. Numerical Land Assignment

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  • 4.2 Alphabetical Signals Reference

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    • Table 25. Signal Description (Sheet 1 of 9)

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• 5 Thermal Specifications and Design Considerations

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  • 5.1 Processor Thermal Specifications

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    • 5.1.1 Thermal Specifications

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      • Table 26. Processor Thermal Specifications

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      • Table 27. Thermal Profile for 775_VR_CONFIG_05B Processors (Performance)

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      • Figure 13. Thermal Profile for 775_VR_CONFIG_05B Processors (Performance)

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      • Table 28. Thermal Profile for 775_VR_CONFIG_05A Processors (Mainstream)

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      • Figure 14. Thermal Profile for 775_VR_CONFIG_05A Processors (Mainstream)

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    • 5.1.2 Thermal Metrology

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      • Figure 15. Case Temperature (TC) Measurement Location

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  • 5.2 Processor Thermal Features

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    • 5.2.1 Thermal Monitor

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    • 5.2.2 On-Demand Mode

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    • 5.2.3 PROCHOT# Signal

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    • 5.2.4 FORCEPR# Signal

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    • 5.2.5 THERMTRIP# Signal

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    • 5.2.6 TCONTROL and Fan Speed Reduction

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    • 5.2.7 Thermal Diode

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      • Table 29. Thermal “Diode” Parameters using Diode Model

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      • Table 30. Thermal “Diode” Parameters using Transistor Model

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      • Table 31. Thermal “Diode” ntrim and Diode_Correction_Offset

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      • Table 32. Thermal Diode Interface

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• 6 Features

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  • 6.1 Power-On Configuration Options

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    • Table 33. Power-On Configuration Option Signals

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  • 6.2 Clock Control and Low Power States

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    • Figure 16. Processor Low Power State Machine

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    • 6.2.1 Normal State

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    • 6.2.2 HALT and Enhanced HALT Powerdown States

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      • 6.2.2.1 HALT Powerdown State

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      • 6.2.2.2 Enhanced HALT Powerdown State

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    • 6.2.3 Stop Grant State

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    • 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Stop Grant Snoop State

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      • 6.2.4.1 HALT Snoop State, Stop Grant Snoop State

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      • 6.2.4.2 Enhanced HALT Snoop State

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    • 6.2.5 Enhanced Intel® SpeedStep® Technology

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• 7 Boxed Processor Specifications

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  • Figure 17. Mechanical Representation of the Boxed Processor

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  • 7.1 Mechanical Specifications

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    • 7.1.1 Boxed Processor Cooling Solution Dimensions

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      • Figure 18. Space Requirements for the Boxed Processor (Side View: applies to all four side views)

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      • Figure 19. Space Requirements for the Boxed Processor (Top View)

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      • Figure 20. Space Requirements for the Boxed Processor (Overall View)

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    • 7.1.2 Boxed Processor Fan Heatsink Weight

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    • 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly

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  • 7.2 Electrical Requirements

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    • 7.2.1 Fan Heatsink Power Supply

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      • Figure 21. Boxed Processor Fan Heatsink Power Cable Connector Description

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      • Table 34. Fan Heatsink Power and Signal Specifications

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      • Figure 22. Baseboard Power Header Placement Relative to Processor Socket

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  • 7.3 Thermal Specifications

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    • 7.3.1 Boxed Processor Cooling Requirements

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      • Figure 23. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 1 View)

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      • Figure 24. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 2 View)

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• 8 Balanced Technology Extended (BTX) Boxed Processor Specifications

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  • Figure 25. Mechanical Representation of the Boxed Processor with a Type I TMA

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  • Figure 26. Mechanical Representation of the Boxed Processor with a Type II TMA

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  • 8.1 Mechanical Specifications

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    • 8.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor Cooling Solution Dimensions

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      • Figure 27. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes

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      • Figure 28. Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume

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    • 8.1.2 Boxed Processor Thermal Module Assembly Weight

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    • 8.1.3 Boxed Processor Support and Retention Module (SRM)

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      • Figure 29. Assembly Stack Including the Support and Retention Module

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  • 8.2 Electrical Requirements

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    • 8.2.1 Thermal Module Assembly Power Supply

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      • Figure 30. Boxed Processor TMA Power Cable Connector Description

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      • Table 35. TMA Power and Signal Specifications

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      • Figure 31. Balanced Technology Extended (BTX) Mainboard Power Header Placement (Hatched Area)

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  • 8.3 Thermal Specifications

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    • 8.3.1 Boxed Processor Cooling Requirements

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    • 8.3.2 Variable Speed Fan

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      • Figure 32. Boxed Processor TMA Set Points

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      • Table 36. TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed Processors

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• 9 Debug Tools Specifications

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  • 9.1 Logic Analyzer Interface (LAI)

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    • 9.1.1 Mechanical Considerations

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    • 9.1.2 Electrical Considerations

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