Microchip Technology Microstick for the 3V PIC24F K-series DM240013-1 사용자 매뉴얼

Microchip Technology

제품 코드

DM240013-1

데이터 시트 (English)데이터 시트 (English)데이터 시트 (English)

데이터 시트 (DM240013-1)

차례

Power Management Modes:
3
High-Performance CPU:
3
Peripheral Features:
3
Analog Features:
3
Special Microcontroller Features:
3
Pin Diagrams
4
Pin Diagrams (Continued)
5
Pin Diagrams (Continued)
6
Table of Contents
7
Most Current Data Sheet
8
Errata
8
Customer Notification System
8
1.0 Device Overview
9
- 1.1 Core Features
  9
- 1.2 Other Special Features
  10
- 1.3 Details on Individual Family Members
  10
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers
17
- 2.1 Basic Connection Requirements
  17
  - FIGURE 2-1: Recommended Minimum connections
    17
- 2.2 Power Supply Pins
  18
- 2.3 Master Clear (MCLR) Pin
  18
  - FIGURE 2-2: Example of MCLR Pin Connections
    18
- 2.4 Voltage Regulator Pin (Vcap)
  19
- 2.5 ICSP Pins
  20
- 2.6 External Oscillator Pins
  21
- 2.7 Unused I/Os
  21
  - FIGURE 2-5: Suggested Placement of the Oscillator Circuit
    21
3.0 CPU
23
- 3.1 Programmer’s Model
  23
- 3.2 CPU Control Registers
  26
  - Register 3-1: SR: ALU STATUS Register
    26
  - Register 3-2: CORCON: CPU Control Register
    27
- 3.3 Arithmetic Logic Unit (ALU)
  27
4.0 Memory Organization
29
- 4.1 Program Address Space
  29
- 4.2 Data Address Space
  31
- 4.3 Interfacing Program and Data Memory Spaces
  41
5.0 Flash Program Memory
45
- 5.1 Table Instructions and Flash Programming
  45
  - FIGURE 5-1: Addressing for Table Registers
    45
- 5.2 RTSP Operation
  46
- 5.3 Enhanced In-Circuit Serial Programming
  46
- 5.4 Control Registers
  46
- 5.5 Programming Operations
  46
  - Register 5-1: NVMCON: Flash Memory Control Register
    47
  - 5.5.1 Programming Algorithm for Flash Program Memory
    48
6.0 Data EEPROM Memory
51
- 6.1 NVMCON Register
  51
- 6.2 NVMKEY Register
  51
  - EXAMPLE 6-1: Data EEPROM Unlock Sequence
    51
  - Register 6-1: NVMCON: Nonvolatile Memory Control Register
    52
- 6.3 NVM Address Register
  53
  - FIGURE 6-1: Data EEPROM Addressing with TBLPAG and NVM Address Registers
    53
- 6.4 Data EEPROM Operations
  53
7.0 Resets
57
- FIGURE 7-1: Reset System Block Diagram
  57
- Register 7-1: RCON: Reset Control Register(1)
  58
- TABLE 7-1: Reset Flag Bit Operation
  59
- 7.1 Clock Source Selection at Reset
  60
  - TABLE 7-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)
    60
- 7.2 Device Reset Times
  60
- 7.3 Special Function Register Reset States
  61
- 7.4 Deep Sleep BOR (DSBOR)
  61
- 7.5 Brown-out Reset (BOR)
  61
8.0 Interrupt Controller
63
- 8.1 Interrupt Vector (IVT) Table
  63
  - 8.1.1 Alternate Interrupt Vector Table (AIVT)
    63
- 8.2 Reset Sequence
  63
- 8.3 Interrupt Control and Status Registers
  66
- 8.4 Interrupt Setup Procedures
  90
9.0 Oscillator Configuration
91
- FIGURE 9-1: PIC24F16KA102 family Clock Diagram
  91
- 9.1 CPU Clocking Scheme
  92
- 9.2 Initial Configuration on POR
  92
  - 9.2.1 Clock Switching Mode Configuration Bits
    92
    - TABLE 9-1: Configuration Bit Values for Clock Selection
      92
- 9.3 Control Registers
  93
- 9.4 Clock Switching Operation
  97
  - 9.4.1 Enabling Clock Switching
    97
  - 9.4.2 Oscillator Switching Sequence
    97
    - EXAMPLE 9-1: Basic Code Sequence For Clock Switching
      98
- 9.5 Reference Clock Output
  98
  - Register 9-4: REFOCON: Reference Oscillator Control Register
    99
10.0 Power-Saving Features
101
- 10.1 Clock Frequency and Clock Switching
  101
- 10.2 Instruction-Based Power-Saving Modes
  101
- 10.3 Doze Mode
  107
- 10.4 Selective Peripheral Module Control
  107
11.0 I/O Ports
113
- 11.1 Parallel I/O (PIO) Ports
  113
  - FIGURE 11-1: Block Diagram of a Typical Shared Port Structure
    113
  - 11.1.1 Open-Drain Configuration
    114
- 11.2 Configuring Analog Port Pins
  114
  - 11.2.1 I/O Port Write/Read Timing
    114
- 11.3 Input Change Notification
  114
  - EXAMPLE 11-1: Port Write/Read Example
    114
12.0 Timer1
115
- FIGURE 12-1: 16-Bit Timer1 Module Block Diagram
  115
- Register 12-1: T1CON: Timer1 Control Register
  116
13.0 Timer2/3
117
- FIGURE 13-1: Timer2/3 (32-Bit) Block Diagram
  118
- FIGURE 13-2: timer2 (16-Bit Synchronous) Block Diagram
  119
- FIGURE 13-3: Timer3 (16-Bit Synchronous) Block Diagram
  119
- Register 13-1: T2CON: Timer2 Control Register
  120
- Register 13-2: T3CON: Timer3 Control Register
  121
14.0 Input Capture
123
- FIGURE 14-1: Input Capture Block Diagram
  123
- 14.1 Input Capture Registers
  124
  - Register 14-1: IC1CON: Input Capture 1 Control Register
    124
15.0 Output Compare
125
- 15.1 Setup for Single Output Pulse Generation
  125
- 15.2 Setup for Continuous Output Pulse Generation
  125
- 15.3 Pulse-Width Modulation (PWM) Mode
  126
  - 15.3.1 PWM Period
    126
    - EQUATION 15-1: Calculating the PWM Period(1)
      126
  - 15.3.2 PWM Duty Cycle
    126
- 15.4 Output Compare Register
  129
  - Register 15-1: OC1CON: Output Compare 1 Control Register
    129
  - Register 15-2: PADCFG1: Pad Configuration Control Register
    130
16.0 Serial Peripheral Interface (SPI)
131
- FIGURE 16-1: SPI1 Module Block Diagram (Standard Buffer Mode)
  132
- FIGURE 16-2: SPI1 Module Block Diagram (Enhanced Buffer Mode)
  133
- Register 16-1: SPI1STAT: SPI1 Status and Control Register
  134
- Register 16-2: SPI1CON1: SPI1 Control Register 1
  136
- Register 16-3: SPI1CON2: SPI1 Control Register 2
  137
- EQUATION 16-1: Relationship Between Device and Spi Clock Speed(1)
  138
- TABLE 16-1: Sample SCK Frequencies(1,2)
  138
17.0 Inter-Integrated Circuit (I2C™)
139
- 17.1 Pin Remapping Options
  139
- 17.2 Communicating as a Master in a Single Master Environment
  139
  - FIGURE 17-1: I2C™ Block Diagram
    140
- 17.3 Setting Baud Rate When Operating as a Bus Master
  141
  - EQUATION 17-1: Computing Baud Rate Reload Value(1)
    141
- 17.4 Slave Address Masking
  141
18.0 Universal Asynchronous Receiver Transmitter (UART)
147
- FIGURE 18-1: UART Simplified Block Diagram
  147
- 18.1 UART Baud Rate Generator (BRG)
  148
- 18.2 Transmitting in 8-Bit Data Mode
  149
- 18.3 Transmitting in 9-Bit Data Mode
  149
- 18.4 Break and Sync Transmit Sequence
  149
- 18.5 Receiving in 8-Bit or 9-Bit Data Mode
  149
- 18.6 Operation of UxCTS and UxRTS Control Pins
  149
- 18.7 Infrared Support
  149
  - 18.7.1 External IrDA Support – IrDA Clock Output
    149
  - 18.7.2 Built-in IrDA Encoder and Decoder
    149
19.0 Real-Time Clock and Calendar (RTCC)
155
- 19.1 RTCC Source Clock
  155
  - FIGURE 19-1: RTCC Block Diagram
    155
- 19.2 RTCC Module Registers
  156
- 19.3 Calibration
  164
  - EQUATION 19-1:
    164
- 19.4 Alarm
  164
  - 19.4.1 Configuring The Alarm
    164
  - 19.4.2 Alarm Interrupt
    164
    - FIGURE 19-2: Alarm Mask Settings
      165
20.0 Programmable Cyclic Redundancy Check (CRC) Generator
167
- EQUATION 20-1: CRC
  167
- TABLE 20-1: Example CRC Setup
  167
- FIGURE 20-1: CRC Shifter Details
  167
- FIGURE 20-2: CRC Generator Reconfigured for x16 + x12 + x5 + 1
  168
- 20.1 User Interface
  168
  - 20.1.1 Data Interface
    168
  - 20.1.2 Interrupt Operation
    168
- 20.2 Operation in Power Save Modes
  168
  - 20.2.1 Sleep Mode
    168
  - 20.2.2 Idle Mode
    168
- 20.3 Registers
  169
  - Register 20-1: CRCCON: CRC Control Register
    169
  - Register 20-2: CRCXOR: CRC XOR Polynomial Register
    170
21.0 High/Low-Voltage Detect (HLVD)
171
- FIGURE 21-1: High/Low-Voltage Detect (HLVD) Module Block Diagram
  171
- Register 21-1: HLVDCON: High/Low-Voltage Detect Control Register
  172
22.0 10-Bit High-Speed A/D Converter
173
- FIGURE 22-1: 10-Bit High-Speed A/D Converter Block Diagram
  174
- Register 22-1: AD1CON1: A/D Control Register 1
  175
- Register 22-2: AD1CON2: A/D Control Register 2
  176
- Register 22-3: AD1CON3: A/D Control Register 3
  177
- Register 22-4: AD1CHS: A/D Input Select Register
  178
- Register 22-5: AD1PCFG: A/D Port Configuration Register
  179
- Register 22-6: AD1CSSL: A/D Input Scan Select Register (Low)
  180
- EQUATION 22-1: A/D Conversion Clock Period(1)
  181
- FIGURE 22-2: 10-bit A/D Converter Analog Input Model
  181
- FIGURE 22-3: A/D Transfer Function
  182
23.0 Comparator Module
183
- FIGURE 23-1: Comparator Module Block Diagram
  183
- FIGURE 23-2: Individual Comparator Configurations
  184
- Register 23-1: CMxCON: Comparator x Control Registers
  185
- Register 23-2: CMSTAT: Comparator Module Status Register
  186
24.0 Comparator Voltage Reference
187
- 24.1 Configuring the Comparator Voltage Reference
  187
  - FIGURE 24-1: Comparator Voltage Reference Block Diagram
    187
  - Register 24-1: CVRCON: Comparator Voltage Reference Control Register
    188
25.0 Charge Time Measurement Unit (CTMU)
189
- 25.1 Measuring Capacitance
  189
  - FIGURE 25-1: Typical Connections and Internal Configuration for Capacitance Measurement
    189
- 25.2 Measuring Time
  190
- 25.3 Pulse Generation and Delay
  190
26.0 Special Features
193
- 26.1 Configuration Bits
  193
- 26.2 Watchdog Timer (WDT)
  201
  - 26.2.1 Windowed Operation
    201
  - 26.2.2 Control Register
    201
    - FIGURE 26-1: WDT Block Diagram
      201
- 26.3 Deep Sleep Watchdog Timer (DSWDT)
  202
- 26.4 Program Verification and Code Protection
  202
- 26.5 In-Circuit Serial Programming
  202
- 26.6 In-Circuit Debugger
  202
- 27.0 Development Support
  203
28.0 Instruction Set Summary
207
- TABLE 28-1: Symbols Used in Opcode Descriptions
  208
- TABLE 28-2: Instruction Set Overview
  209
29.0 Electrical Characteristics
215
- Absolute Maximum Ratings(†)
  215
- 29.1 DC Characteristics
  216
- 29.2 AC Characteristics and Timing Parameters
  231
30.0 Packaging Information
251
- 30.1 Package Marking Information
  251
- 30.2 Package Details
  253
Appendix A: Revision History
269
- Revision A (November 2008)
  269
- Revision B (March 2009)
  269
- Revision C (October 2011)
  269
INDEX
271
The Microchip Web Site
275
Customer Change Notification Service
275
Customer Support
275
Reader Response
276
Product Identification System
277
Worldwide Sales and Service
278

데이터 시트 (DM240013-1)

크기:

2.55메가바이트
페이지:

278
Language:

English

매뉴얼 열기

데이터 시트 (DM240013-1)

차례

데이터 시트 (DM240013-1)

크기:

3.16메가바이트
페이지:

260
Language:

English

매뉴얼 열기

데이터 시트 (DM240013-1)

데이터 시트 (DM240013-1)

크기:

189킬로바이트
페이지:

4
Language:

English

매뉴얼 열기