Техническая Спецификация (DM240013-1)СодержаниеPower Management Modes:3High-Performance CPU:3Peripheral Features:3Analog Features:3Special Microcontroller Features:3Pin Diagrams4Pin Diagrams (Continued)5Pin Diagrams (Continued)6Table of Contents7Most Current Data Sheet8Errata8Customer Notification System81.0 Device Overview91.1 Core Features91.1.1 16-bit architecture91.1.2 Power-saving Technology91.1.3 Oscillator Options and Features91.1.4 Easy Migration101.2 Other Special Features101.3 Details on Individual Family Members10TABLE 1-1: Device Features for the PIC24F16KA102 family11FIGURE 1-1: PIC24F16KA102 family General Block Diagram12TABLE 1-2: PIC24F16KA102 family Pinout Descriptions132.0 Guidelines for Getting Started with 16-Bit Microcontrollers172.1 Basic Connection Requirements17FIGURE 2-1: Recommended Minimum connections172.2 Power Supply Pins182.3 Master Clear (MCLR) Pin18FIGURE 2-2: Example of MCLR Pin Connections182.4 Voltage Regulator Pin (Vcap)19FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap19TABLE 2-1: Suitable Capacitor Equivalents19FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics202.5 ICSP Pins202.6 External Oscillator Pins212.7 Unused I/Os21FIGURE 2-5: Suggested Placement of the Oscillator Circuit213.0 CPU233.1 Programmer’s Model23FIGURE 3-1: PIC24F CPU Core Block Diagram24TABLE 3-1: CPU Core Registers24FIGURE 3-2: Programmer’s Model253.2 CPU Control Registers26Register 3-1: SR: ALU STATUS Register26Register 3-2: CORCON: CPU Control Register273.3 Arithmetic Logic Unit (ALU)273.3.1 Multiplier273.3.2 Divider283.3.3 Multi-Bit Shift Support28TABLE 3-2: Instructions that Use the Single and Multi-Bit Shift Operation284.0 Memory Organization294.1 Program Address Space29FIGURE 4-1: Program Space Memory Map for PIC24F16KA102 family Devices294.1.1 Program Memory Organization304.1.2 Hard Memory Vectors304.1.3 Data EEPROM304.1.4 Device Configuration Words30TABLE 4-1: Device Configuration Words for PIC24F16KA102 family Devices30FIGURE 4-2: Program Memory Organization304.2 Data Address Space314.2.1 Data Space Width31FIGURE 4-3: Data Space Memory Map for PIC24F16KA102 family Devices314.2.2 Data Memory Organization and Alignment324.2.3 Near Data Space324.2.4 SFR Space32TABLE 4-2: Implemented Regions of SFR Data Space32TABLE 4-3: CPU Core Registers Map33TABLE 4-4: ICN Register Map34TABLE 4-5: Interrupt Controller Register Map34TABLE 4-6: Timer Register Map35TABLE 4-7: Input Capture Register Map35TABLE 4-8: Output Compare Register Map35TABLE 4-9: I2C™ Register Map36TABLE 4-10: UART Register Map36TABLE 4-11: SPI Register Map36TABLE 4-12: PORTA Register Map37TABLE 4-13: PORTB Register Map37TABLE 4-14: Pad Configuration Register Map37TABLE 4-15: A/D Register Map38TABLE 4-16: CTMU Register Map38TABLE 4-17: Real-Time Clock and Calendar Register Map39TABLE 4-18: Dual Comparator Register Map39TABLE 4-19: CRC Register Map39TABLE 4-20: Clock Control Register Map40TABLE 4-21: Deep Sleep Register Map40TABLE 4-22: NVM Register Map40TABLE 4-23: PMD Register Map404.2.5 Software Stack41FIGURE 4-4: CALL Stack Frame414.3 Interfacing Program and Data Memory Spaces414.3.1 Addressing Program Space41TABLE 4-24: Program Space Address Construction42FIGURE 4-5: Data Access From Program Space Address Generation424.3.2 Data Access From Program Memory and Data EEPROM Memory Using Table Instructions43FIGURE 4-6: Accessing Program Memory with Table Instructions434.3.3 Reading Data From Program Memory Using Program Space Visibility44FIGURE 4-7: Program Space Visibility Operation445.0 Flash Program Memory455.1 Table Instructions and Flash Programming45FIGURE 5-1: Addressing for Table Registers455.2 RTSP Operation465.3 Enhanced In-Circuit Serial Programming465.4 Control Registers465.5 Programming Operations46Register 5-1: NVMCON: Flash Memory Control Register475.5.1 Programming Algorithm for Flash Program Memory48EXAMPLE 5-1: Erasing a Program Memory Row – Assembly Language Code48EXAMPLE 5-2: Erasing a Program Memory Row – ‘C’ Language Code48EXAMPLE 5-3: Loading the Write Buffers – Assembly Language Code49EXAMPLE 5-4: Loading the Write Buffers – ‘C’ Language Code49EXAMPLE 5-5: Initiating a Programming Sequence – Assembly Language Code50EXAMPLE 5-6: Initiating a Programming Sequence – ‘C’ Language Code506.0 Data EEPROM Memory516.1 NVMCON Register516.2 NVMKEY Register51EXAMPLE 6-1: Data EEPROM Unlock Sequence51Register 6-1: NVMCON: Nonvolatile Memory Control Register526.3 NVM Address Register53FIGURE 6-1: Data EEPROM Addressing with TBLPAG and NVM Address Registers536.4 Data EEPROM Operations536.4.1 Erase Data EEPROM54EXAMPLE 6-2: Single-Word Erase546.4.2 Single-Word Write55EXAMPLE 6-3: Data EEPROM Bulk Erase55EXAMPLE 6-4: Single-Word Write to Data EEPROM556.4.3 Reading the Data EEPROM56EXAMPLE 6-5: Reading the Data EEPROM Using the TBLRD Command567.0 Resets57FIGURE 7-1: Reset System Block Diagram57Register 7-1: RCON: Reset Control Register(1)58TABLE 7-1: Reset Flag Bit Operation597.1 Clock Source Selection at Reset60TABLE 7-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)607.2 Device Reset Times60TABLE 7-3: Reset Delay Times for Various Device Resets607.2.1 POR and Long Oscillator Start-up Times617.2.2 Fail-Safe Clock Monitor (FSCM) and Device Resets617.3 Special Function Register Reset States617.4 Deep Sleep BOR (DSBOR)617.5 Brown-out Reset (BOR)617.5.1 Software Enabled BOR617.5.2 Detecting BOR627.5.3 Disabling BOR in Sleep Mode628.0 Interrupt Controller638.1 Interrupt Vector (IVT) Table638.1.1 Alternate Interrupt Vector Table (AIVT)638.2 Reset Sequence63FIGURE 8-1: PIC24F Interrupt Vector Table64TABLE 8-1: Trap Vector Details65TABLE 8-2: Implemented Interrupt Vectors658.3 Interrupt Control and Status Registers66Register 8-1: SR: ALU STATUS Register67Register 8-2: CORCON: CPU Control Register68Register 8-3: INTCON1: Interrupt Control Register 169Register 8-4: INTCON2: Interrupt Control Register270Register 8-5: IFS0: Interrupt Flag Status Register 071Register 8-6: IFS1: Interrupt Flag Status Register 172Register 8-7: IFS3: Interrupt Flag Status Register 373Register 8-8: IFS4: Interrupt Flag Status Register 474Register 8-9: IEC0: Interrupt Enable Control Register 075Register 8-10: IEC1: Interrupt Enable Control Register 176Register 8-11: IEC3: Interrupt Enable Control Register 377Register 8-12: IEC4: Interrupt Enable Control Register 478Register 8-13: IPC0: Interrupt Priority Control Register 079Register 8-14: IPC1: Interrupt Priority Control Register 180Register 8-15: IPC2: Interrupt Priority Control Register 281Register 8-16: IPC3: Interrupt Priority Control Register 382Register 8-17: IPC4: Interrupt Priority Control Register 483Register 8-18: IPC5: Interrupt Priority Control Register 584Register 8-19: IPC7: Interrupt Priority Control Register 785Register 8-20: IPC15: Interrupt Priority Control Register 1586Register 8-21: IPC16: Interrupt Priority Control Register 1687Register 8-22: IPC18: Interrupt Priority Control Register 1888Register 8-23: IPC19: Interrupt Priority Control Register 1988Register 8-24: INTTREG: Interrupt Control and Status Register898.4 Interrupt Setup Procedures908.4.1 Initialization908.4.2 Interrupt Service Routine908.4.3 Trap Service Routine (TSR)908.4.4 Interrupt Disable909.0 Oscillator Configuration91FIGURE 9-1: PIC24F16KA102 family Clock Diagram919.1 CPU Clocking Scheme929.2 Initial Configuration on POR929.2.1 Clock Switching Mode Configuration Bits92TABLE 9-1: Configuration Bit Values for Clock Selection929.3 Control Registers93Register 9-1: OSCCON: Oscillator Control Register93Register 9-2: CLKDIV: Clock Divider Register95Register 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER969.4 Clock Switching Operation979.4.1 Enabling Clock Switching979.4.2 Oscillator Switching Sequence97EXAMPLE 9-1: Basic Code Sequence For Clock Switching989.5 Reference Clock Output98Register 9-4: REFOCON: Reference Oscillator Control Register9910.0 Power-Saving Features10110.1 Clock Frequency and Clock Switching10110.2 Instruction-Based Power-Saving Modes10110.2.1 Sleep Mode101EXAMPLE 10-1: PWRSAV Instruction Syntax10110.2.2 Idle Mode10210.2.3 Interrupts Coincident with Power Save Instructions10210.2.4 Deep Sleep Mode102Register 10-1: DSCON: Deep Sleep Control Register(1)105Register 10-2: DSWAKE: Deep Sleep Wake-Up Source Register(1)10610.3 Doze Mode10710.4 Selective Peripheral Module Control107Register 10-3: PMD1: Peripheral Module Disable Register 1108Register 10-4: PMD2: Peripheral Module Disable Register 2109Register 10-5: PMD3: Peripheral Module Disable Register 3110Register 10-6: PMD4: Peripheral Module Disable Register 411111.0 I/O Ports11311.1 Parallel I/O (PIO) Ports113FIGURE 11-1: Block Diagram of a Typical Shared Port Structure11311.1.1 Open-Drain Configuration11411.2 Configuring Analog Port Pins11411.2.1 I/O Port Write/Read Timing11411.3 Input Change Notification114EXAMPLE 11-1: Port Write/Read Example11412.0 Timer1115FIGURE 12-1: 16-Bit Timer1 Module Block Diagram115Register 12-1: T1CON: Timer1 Control Register11613.0 Timer2/3117FIGURE 13-1: Timer2/3 (32-Bit) Block Diagram118FIGURE 13-2: timer2 (16-Bit Synchronous) Block Diagram119FIGURE 13-3: Timer3 (16-Bit Synchronous) Block Diagram119Register 13-1: T2CON: Timer2 Control Register120Register 13-2: T3CON: Timer3 Control Register12114.0 Input Capture123FIGURE 14-1: Input Capture Block Diagram12314.1 Input Capture Registers124Register 14-1: IC1CON: Input Capture 1 Control Register12415.0 Output Compare12515.1 Setup for Single Output Pulse Generation12515.2 Setup for Continuous Output Pulse Generation12515.3 Pulse-Width Modulation (PWM) Mode12615.3.1 PWM Period126EQUATION 15-1: Calculating the PWM Period(1)12615.3.2 PWM Duty Cycle126EQUATION 15-2: Calculation for Maximum PWM Resolution(1)126EXAMPLE 15-1: PWM Period and Duty Cycle Calculations(1)127TABLE 15-1: Example PWM Frequencies and Resolutions at 4 MIPS (Fcy = 4 MHz)(1)127TABLE 15-2: Example PWM Frequencies and Resolutions at 16 MIPS (Fcy = 16 MHz)(1)127FIGURE 15-1: Output Compare Module Block Diagram12815.4 Output Compare Register129Register 15-1: OC1CON: Output Compare 1 Control Register129Register 15-2: PADCFG1: Pad Configuration Control Register13016.0 Serial Peripheral Interface (SPI)131FIGURE 16-1: SPI1 Module Block Diagram (Standard Buffer Mode)132FIGURE 16-2: SPI1 Module Block Diagram (Enhanced Buffer Mode)133Register 16-1: SPI1STAT: SPI1 Status and Control Register134Register 16-2: SPI1CON1: SPI1 Control Register 1136Register 16-3: SPI1CON2: SPI1 Control Register 2137EQUATION 16-1: Relationship Between Device and Spi Clock Speed(1)138TABLE 16-1: Sample SCK Frequencies(1,2)13817.0 Inter-Integrated Circuit (I2C™)13917.1 Pin Remapping Options13917.2 Communicating as a Master in a Single Master Environment139FIGURE 17-1: I2C™ Block Diagram14017.3 Setting Baud Rate When Operating as a Bus Master141EQUATION 17-1: Computing Baud Rate Reload Value(1)14117.4 Slave Address Masking141TABLE 17-1: I2C™ Clock Rates(1)141TABLE 17-2: I2C™ Reserved Addresses(1)141Register 17-1: I2C1CON: I2C1 Control Register142Register 17-2: I2C1STAT: I2C1 Status Register144Register 17-3: I2C1MSK: I2C1 Slave Mode Address Mask Register146Register 17-4: PADCFG1: Pad Configuration Control Register14618.0 Universal Asynchronous Receiver Transmitter (UART)147FIGURE 18-1: UART Simplified Block Diagram14718.1 UART Baud Rate Generator (BRG)148EQUATION 18-1: UART Baud Rate with BRGH = 0(1)148EQUATION 18-2: UART Baud Rate with BRGH = 1(1)148EXAMPLE 18-1: Baud Rate Error Calculation (BRGH = 0)(1)14818.2 Transmitting in 8-Bit Data Mode14918.3 Transmitting in 9-Bit Data Mode14918.4 Break and Sync Transmit Sequence14918.5 Receiving in 8-Bit or 9-Bit Data Mode14918.6 Operation of UxCTS and UxRTS Control Pins14918.7 Infrared Support14918.7.1 External IrDA Support – IrDA Clock Output14918.7.2 Built-in IrDA Encoder and Decoder149Register 18-1: UxMODE: UARTx Mode Register150Register 18-2: UxSTA: UARTx Status and Control Register152Register 18-3: UxTXREG: UARTx Transmit Register154Register 18-4: UxRXREG: UARTx Receive Register15419.0 Real-Time Clock and Calendar (RTCC)15519.1 RTCC Source Clock155FIGURE 19-1: RTCC Block Diagram15519.2 RTCC Module Registers15619.2.1 Register Mapping156TABLE 19-1: RTCVAL Register Mapping156TABLE 19-2: ALRMVAL Register Mapping15619.2.2 Write Lock15619.2.3 Selecting RTCC Clock Source156EXAMPLE 19-1: Setting the RTCWREN Bit15619.2.4 RTCC Control Registers157Register 19-1: RCFGCAL: RTCC Calibration and Configuration Register(1)157Register 19-2: PADCFG1: Pad Configuration Control Register158Register 19-3: ALCFGRPT: Alarm Configuration Register15919.2.5 RTCVAL Register Mappings160Register 19-4: YEAR: Year Value Register(1)160Register 19-5: MTHDY: Month and Day Value Register(1)160Register 19-6: WKDYHR: Weekday and Hours Value Register(1)161Register 19-7: MINSEC: Minutes and Seconds Value Register16119.2.6 ALRMVAL Register Mappings162Register 19-8: ALMTHDY: Alarm Month and Day Value Register(1)162Register 19-9: ALWDHR: Alarm Weekday and Hours Value Register(1)162Register 19-10: ALMINSEC: Alarm Minutes and Seconds Value Register16319.3 Calibration164EQUATION 19-1:16419.4 Alarm16419.4.1 Configuring The Alarm16419.4.2 Alarm Interrupt164FIGURE 19-2: Alarm Mask Settings16520.0 Programmable Cyclic Redundancy Check (CRC) Generator167EQUATION 20-1: CRC167TABLE 20-1: Example CRC Setup167FIGURE 20-1: CRC Shifter Details167FIGURE 20-2: CRC Generator Reconfigured for x16 + x12 + x5 + 116820.1 User Interface16820.1.1 Data Interface16820.1.2 Interrupt Operation16820.2 Operation in Power Save Modes16820.2.1 Sleep Mode16820.2.2 Idle Mode16820.3 Registers169Register 20-1: CRCCON: CRC Control Register169Register 20-2: CRCXOR: CRC XOR Polynomial Register17021.0 High/Low-Voltage Detect (HLVD)171FIGURE 21-1: High/Low-Voltage Detect (HLVD) Module Block Diagram171Register 21-1: HLVDCON: High/Low-Voltage Detect Control Register17222.0 10-Bit High-Speed A/D Converter173FIGURE 22-1: 10-Bit High-Speed A/D Converter Block Diagram174Register 22-1: AD1CON1: A/D Control Register 1175Register 22-2: AD1CON2: A/D Control Register 2176Register 22-3: AD1CON3: A/D Control Register 3177Register 22-4: AD1CHS: A/D Input Select Register178Register 22-5: AD1PCFG: A/D Port Configuration Register179Register 22-6: AD1CSSL: A/D Input Scan Select Register (Low)180EQUATION 22-1: A/D Conversion Clock Period(1)181FIGURE 22-2: 10-bit A/D Converter Analog Input Model181FIGURE 22-3: A/D Transfer Function18223.0 Comparator Module183FIGURE 23-1: Comparator Module Block Diagram183FIGURE 23-2: Individual Comparator Configurations184Register 23-1: CMxCON: Comparator x Control Registers185Register 23-2: CMSTAT: Comparator Module Status Register18624.0 Comparator Voltage Reference18724.1 Configuring the Comparator Voltage Reference187FIGURE 24-1: Comparator Voltage Reference Block Diagram187Register 24-1: CVRCON: Comparator Voltage Reference Control Register18825.0 Charge Time Measurement Unit (CTMU)18925.1 Measuring Capacitance189FIGURE 25-1: Typical Connections and Internal Configuration for Capacitance Measurement18925.2 Measuring Time19025.3 Pulse Generation and Delay190FIGURE 25-2: Typical Connections and Internal Configuration for Time Measurement190FIGURE 25-3: Typical Connections and Internal Configuration for Pulse Delay Generation190Register 25-1: CTMUCON: CTMU Control Register191Register 25-2: CTMUICON: CTMU current Control Register19226.0 Special Features19326.1 Configuration Bits193TABLE 26-1: CONFIGURATION Registers LOCATIONS193Register 26-1: FBS: Boot Segment Configuration Register193Register 26-2: FGS: General Segment Configuration Register194Register 26-3: FoscSEL: Oscillator Selection Configuration Register194Register 26-4: Fosc: Oscillator Configuration Register195Register 26-5: FWDT: Watchdog Timer Configuration Register196Register 26-6: FPOR: Reset Configuration Register197Register 26-7: FICD: In-Circuit Debugger Configuration Register198Register 26-8: FDS: Deep Sleep Configuration Register199Register 26-9: DEVID: Device ID Register200Register 26-10: DEVREV: Device Revision Register20026.2 Watchdog Timer (WDT)20126.2.1 Windowed Operation20126.2.2 Control Register201FIGURE 26-1: WDT Block Diagram20126.3 Deep Sleep Watchdog Timer (DSWDT)20226.4 Program Verification and Code Protection20226.5 In-Circuit Serial Programming20226.6 In-Circuit Debugger20227.0 Development Support20328.0 Instruction Set Summary207TABLE 28-1: Symbols Used in Opcode Descriptions208TABLE 28-2: Instruction Set Overview20929.0 Electrical Characteristics215Absolute Maximum Ratings(†)21529.1 DC Characteristics216FIGURE 29-1: PIC24F16KA102 family Voltage-Frequency Graph (Industrial)216FIGURE 29-2: PIC24F16KA102 family Voltage-frequency Graph (Industrial, Extended)216TABLE 29-1: Thermal Operating Conditions217TABLE 29-2: Thermal Packaging Characteristics217TABLE 29-3: DC Characteristics: Temperature and Voltage Specifications218TABLE 29-4: High/Low–Voltage Detect Characteristics218FIGURE 29-3: BROWN-OUT RESET CHARACTERISTICS219TABLE 29-5: BOR Trip Points219TABLE 29-6: DC Characteristics: Operating Current (Idd)220TABLE 29-7: DC Characteristics: Idle Current (Iidle)222TABLE 29-8: DC Characteristics: Power-Down Current (Ipd)224TABLE 29-9: DC Characteristics: I/O Pin Input Specifications227TABLE 29-10: DC Characteristics: I/O Pin Output Specifications228TABLE 29-11: DC Characteristics: Program Memory229TABLE 29-12: DC Characteristics: Data EEPROM Memory229TABLE 29-13: Comparator DC Specifications230TABLE 29-14: Comparator Voltage Reference DC Specifications230TABLE 29-15: Internal Voltage References230TABLE 29-16: CTMU Current Source Specifications23029.2 AC Characteristics and Timing Parameters231TABLE 29-17: Temperature and Voltage Specifications – AC231FIGURE 29-4: Load Conditions for Device Timing Specifications231TABLE 29-18: Capacitive Loading Requirements on Output Pins231FIGURE 29-5: External Clock Timing232TABLE 29-19: External Clock Timing Requirements232TABLE 29-20: PLL Clock Timing Specifications (Vdd = 1.8V to 3.6V)233TABLE 29-21: AC Characteristics: Internal RC Accuracy233TABLE 29-22: AC Specifications234TABLE 29-23: A/D Conversion TiminG Requirements(1)234TABLE 29-24: A/D Module Specifications235FIGURE 29-6: CLKO and I/O Timing Characteristics236TABLE 29-25: CLKO and I/O Timing Requirements236TABLE 29-26: Comparator Timings237TABLE 29-27: Comparator Voltage Reference Settling Time Specifications237FIGURE 29-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics238TABLE 29-28: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Timing Requirements239FIGURE 29-8: Baud Rate Generator Output Timing239FIGURE 29-9: I2C™ Bus Start/Stop Bits Timing Characteristics (Master Mode)240TABLE 29-29: I2C™ Bus Start/Stop Bit Timing Requirements (Master Mode)240FIGURE 29-10: I2C™ Bus Data Timing Characteristics (Master Mode)240TABLE 29-30: I2C™ Bus Data Timing Requirements (Master Mode)241FIGURE 29-11: I2C™ Bus Start/Stop Bits Timing Characteristics (Slave Mode)242FIGURE 29-12: I2C™ Bus Data Timing Characteristics (Slave Mode)242TABLE 29-31: I2C™ Bus Start/Stop Bit Timing Requirements (Slave Mode)242TABLE 29-32: I2C™ Bus Data Timing Requirements (Slave Mode)243FIGURE 29-13: Start Bit Edge Detection243FIGURE 29-14: Input Capture Timings244TABLE 29-33: Input Capture244TABLE 29-34: Output Capture244FIGURE 29-15: Output Compare Timings244FIGURE 29-16: PWM Module Timing Requirements245TABLE 29-35: PWM Timing Requirements245FIGURE 29-17: SPIx Module Master Mode Timing Characteristics (CKE = 0)246TABLE 29-36: SPIx Master Mode Timing Requirements (CKE = 0)246FIGURE 29-18: SPIx Module Master Mode Timing Characteristics (CKE = 1)247TABLE 29-37: SPIx Module Master Mode Timing Requirements (CKE = 1)247FIGURE 29-19: SPIx Module Slave Mode Timing Characteristics (CKE = 0)248TABLE 29-38: SPIx Module Slave Mode Timing Requirements (CKE = 0)248FIGURE 29-20: SPIx Module Slave Mode Timing Characteristics (CKE = 1)249TABLE 29-39: SPIx Module Slave Mode Timing Requirements (CKE = 1)24930.0 Packaging Information25130.1 Package Marking Information25130.2 Package Details253Appendix A: Revision History269Revision A (November 2008)269Revision B (March 2009)269Revision C (October 2011)269INDEX271The Microchip Web Site275Customer Change Notification Service275Customer Support275Reader Response276Product Identification System277Worldwide Sales and Service278Размер: 2,5 МБСтраницы: 278Язык: EnglishПросмотреть
Техническая Спецификация (DM240013-1)СодержаниеPower Management Modes:1High-Performance CPU:1Peripheral Features:1Analog Features:2Special Microcontroller Features:2Pin Diagrams: PIC24FXXKL302/4023Pin Diagrams: PIC24FXXKL301/4014Table of Contents6Most Current Data Sheet7Errata7Customer Notification System71.0 Device Overview91.1 Core Features91.1.1 16-bit architecture91.1.2 Power-saving Technology91.1.3 Oscillator Options and Features91.1.4 Easy Migration91.2 Other Special Features101.3 Details on Individual Family Members10TABLE 1-1: Feature Comparison for PIC24F16KL402 Family Groups10TABLE 1-2: Device Features for PIC24F16KL40X/30X Devices11TABLE 1-3: Device Features for the PIC24F16KL20X/10X Devices12FIGURE 1-1: PIC24F16KL402 Family General Block Diagram13TABLE 1-4: PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS14TABLE 1-5: PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS182.0 Guidelines for Getting Started with 16-Bit Microcontrollers212.1 Basic Connection Requirements21FIGURE 2-1: Recommended Minimum connections212.2 Power Supply Pins222.2.1 Decoupling Capacitors222.2.2 Tank Capacitors222.3 Master Clear (MCLR) Pin22FIGURE 2-2: Example of MCLR Pin Connections222.4 ICSP Pins232.5 External Oscillator Pins23FIGURE 2-3: Suggested Placement of the Oscillator Circuit232.6 Unused I/Os243.0 CPU253.1 Programmer’s Model25FIGURE 3-1: PIC24F CPU Core Block Diagram26TABLE 3-1: CPU Core Registers26FIGURE 3-2: Programmer’s Model273.2 CPU Control Registers28Register 3-1: SR: ALU STATUS Register28Register 3-2: CORCON: CPU Control Register293.3 Arithmetic Logic Unit (ALU)293.3.1 Multiplier293.3.2 Divider303.3.3 Multi-Bit Shift Support30TABLE 3-2: Instructions that Use the Single and Multi-Bit Shift Operation304.0 Memory Organization314.1 Program Address Space31FIGURE 4-1: Program Space Memory Map for PIC24F16KL402 Family Devices314.1.1 Program Memory Organization324.1.2 Hard Memory Vectors324.1.3 Data EEPROM324.1.4 Device Configuration Words32TABLE 4-1: Device Configuration Words for PIC24F16KL402 Family Devices32FIGURE 4-2: Program Memory Organization324.2 Data Address Space334.2.1 Data Space Width33FIGURE 4-3: Data Space Memory Map for PIC24F16KL402 Family Devices(3)334.2.2 Data Memory Organization and Alignment344.2.3 Near Data Space344.2.4 SFR Space34TABLE 4-2: Implemented Regions of SFR Data Space34TABLE 4-3: CPU CORE REGISTERS MAP35TABLE 4-4: ICN Register Map36TABLE 4-5: Interrupt Controller Register Map37TABLE 4-6: Timer Register Map38TABLE 4-7: CCP/ECCP Register Map38TABLE 4-8: MSSP Register Map39TABLE 4-9: UART Register Map39TABLE 4-10: PORTA Register Map40TABLE 4-11: PORTB Register Map40TABLE 4-12: Pad Configuration Register Map40TABLE 4-13: A/D Register Map41TABLE 4-14: Analog Select Register Map41TABLE 4-15: Comparator Register Map41TABLE 4-16: System Register Map42TABLE 4-17: NVM Register Map42TABLE 4-18: Ultra Low-Power Wake-up Register Map42TABLE 4-19: PMD Register Map424.2.5 Software Stack43FIGURE 4-4: CALL Stack Frame434.3 Interfacing Program and Data Memory Spaces434.3.1 Addressing Program Space43TABLE 4-20: Program Space Address Construction44FIGURE 4-5: Data Access From Program Space Address Generation444.3.2 Data Access From Program Memory and Data EEPROM Memory Using Table Instructions45FIGURE 4-6: Accessing Program Memory with Table Instructions454.3.3 Reading Data From Program Memory Using Program Space Visibility46FIGURE 4-7: Program Space Visibility Operation465.0 Flash Program Memory475.1 Table Instructions and Flash Programming47FIGURE 5-1: Addressing for Table Registers475.2 RTSP Operation485.3 Enhanced In-Circuit Serial Programming485.4 Control Registers485.5 Programming Operations48Register 5-1: NVMCON: Flash Memory Control Register495.5.1 Programming Algorithm for Flash Program Memory50EXAMPLE 5-1: Erasing a Program Memory Row – Assembly Language Code50EXAMPLE 5-2: Erasing a Program Memory Row – ‘C’ Language Code51EXAMPLE 5-3: Loading the Write Buffers – Assembly Language Code51EXAMPLE 5-4: Loading the Write Buffers – ‘C’ Language Code52EXAMPLE 5-5: Initiating a Programming Sequence – Assembly Language Code52EXAMPLE 5-6: Initiating a Programming Sequence – ‘C’ Language Code526.0 Data EEPROM Memory536.1 NVMCON Register536.2 NVMKEY Register53EXAMPLE 6-1: Data EEPROM Unlock Sequence53Register 6-1: NVMCON: Nonvolatile Memory Control Register546.3 NVM Address Register55FIGURE 6-1: Data EEPROM Addressing with TBLPAG and NVM Address Registers556.4 Data EEPROM Operations556.4.1 Erase Data EEPROM56EXAMPLE 6-2: Single-Word Erase566.4.2 Single-Word Write57EXAMPLE 6-3: Data EEPROM Bulk Erase57EXAMPLE 6-4: Single-Word Write to Data EEPROM576.4.3 Reading the Data EEPROM58EXAMPLE 6-5: Reading the Data EEPROM Using the TBLRD Command587.0 Resets59FIGURE 7-1: Reset System Block Diagram59Register 7-1: RCON: Reset Control Register(1)60TABLE 7-1: Reset Flag Bit Operation617.1 Clock Source Selection at Reset61TABLE 7-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)617.2 Device Reset Times62TABLE 7-3: Reset Delay Times for Various Device Resets627.2.1 POR and Long Oscillator Start-up Times637.2.2 Fail-Safe Clock Monitor (FSCM) and Device Resets637.3 Special Function Register Reset States637.4 Brown-out Reset (BOR)637.4.1 Software Enabled BOR637.4.2 Detecting BOR647.4.3 Disabling BOR in Sleep Mode648.0 Interrupt Controller658.1 Interrupt Vector Table (IVT)658.1.1 Alternate Interrupt Vector Table (AIVT)658.2 Reset Sequence65FIGURE 8-1: PIC24F Interrupt Vector Table66TABLE 8-1: Trap Vector Details67TABLE 8-2: Implemented Interrupt Vectors678.3 Interrupt Control and Status Registers68Register 8-1: SR: ALU STATUS Register69Register 8-2: CORCON: CPU Control Register70Register 8-3: INTCON1: Interrupt Control Register 171Register 8-4: INTCON2: Interrupt Control Register272Register 8-5: IFS0: Interrupt Flag Status Register 073Register 8-6: IFS1: Interrupt Flag Status Register 174Register 8-7: IFS2: Interrupt Flag Status Register 275Register 8-8: IFS3: Interrupt Flag Status Register 375Register 8-9: IFS4: Interrupt Flag Status Register 476Register 8-10: IFS5: Interrupt Flag Status Register 576Register 8-11: IEC0: Interrupt Enable Control Register 077Register 8-12: IEC1: Interrupt Enable Control Register 178Register 8-13: IEC2: Interrupt Enable Control Register 279Register 8-14: IEC3: Interrupt Enable Control Register 379Register 8-15: IEC4: Interrupt Enable Control Register 480Register 8-16: Iec5: Interrupt ENABLE CONTROL Register 580Register 8-17: IPC0: Interrupt Priority Control Register 081Register 8-18: IPC1: Interrupt Priority Control Register 182Register 8-19: IPC2: Interrupt Priority Control Register 283Register 8-20: IPC3: Interrupt Priority Control Register 384Register 8-21: IPC4: Interrupt Priority Control Register 485Register 8-22: IPC5: Interrupt Priority Control Register 586Register 8-23: IPC6: Interrupt Priority Control Register 687Register 8-24: IPC7: Interrupt Priority Control Register 788Register 8-25: IPC9: Interrupt Priority Control Register 989Register 8-26: IPC12: Interrupt Priority Control Register 1290Register 8-27: IPC16: Interrupt Priority Control Register 1691Register 8-28: IPC18: Interrupt Priority Control Register 1892Register 8-29: IPC20: Interrupt Priority Control Register 2092Register 8-30: INTTREG: Interrupt Control and Status Register938.4 Interrupt Setup Procedures948.4.1 Initialization948.4.2 Interrupt Service Routine948.4.3 Trap Service Routine (TSR)948.4.4 Interrupt Disable949.0 Oscillator Configuration95FIGURE 9-1: PIC24F16KL402 Family Clock Diagram959.1 CPU Clocking Scheme969.2 Initial Configuration on POR969.2.1 Clock Switching Mode Configuration Bits96TABLE 9-1: Configuration Bit Values for Clock Selection969.3 Control Registers97Register 9-1: OSCCON: Oscillator Control Register97Register 9-2: CLKDIV: Clock Divider Register99Register 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER1009.4 Clock Switching Operation1019.4.1 Enabling Clock Switching1019.4.2 Oscillator Switching Sequence101EXAMPLE 9-1: Basic Code Sequence For Clock Switching1029.5 Reference Clock Output102Register 9-4: REFOCON: Reference Oscillator Control Register10310.0 Power-Saving Features10510.1 Clock Frequency and Clock Switching10510.2 Instruction-Based Power-Saving Modes105EXAMPLE 10-1: PWRSAV Instruction Syntax10510.2.1 Sleep Mode10610.2.2 Idle Mode10610.2.3 Interrupts Coincident with Power Save Instructions10610.3 Ultra Low-Power Wake-up107FIGURE 10-1: Serial Resistor107EXAMPLE 10-2: ULTRA LOW-POWER WAKE-UP INITIALIZATION107Register 10-1: ULPWCON: ULPWU Control Register10810.4 Doze Mode10910.5 Selective Peripheral Module Control10911.0 I/O Ports11111.1 Parallel I/O (PIO) Ports111FIGURE 11-1: Block Diagram of a Typical Shared Port Structure11111.1.1 Open-Drain Configuration11211.1.2 I/O Port Write/Read Timing11211.2 Configuring Analog Port Pins11211.2.1 ANALOG SELECTION REGISTER112Register 11-1: ANSA: Analog Selection (PORTA)113Register 11-2: ANSB: Analog Selection (PORTB)11311.3 Input Change Notification114EXAMPLE 11-1: Port Write/Read Example (Assembly Language)114EXAMPLE 11-2: Port Write/Read Example (C Language)11412.0 Timer1115FIGURE 12-1: 16-Bit Timer1 Module Block Diagram115Register 12-1: T1CON: Timer1 Control Register11613.0 Timer2 Module117FIGURE 13-1: Timer2 Block Diagram117Register 13-1: T2CON: Timer2 Control Register11814.0 Timer3 Module119FIGURE 14-1: Timer3 Block Diagram119Register 14-1: T3CON: Timer3 Control Register120Register 14-2: T3GCON: Timer3 Gate Control Register(1)12115.0 Timer4 Module123FIGURE 15-1: Timer4 Block Diagram123Register 15-1: T4CON: Timer4 Control Register12416.0 Capture/Compare/PWM (CCP) and Enhanced CCP Modules12516.1 Timer Selection12516.2 CCP I/O Pins125FIGURE 16-1: Generic Capture Mode Block Diagram126FIGURE 16-2: Generic Compare Mode Block Diagram126FIGURE 16-3: Simplified PWM Block Diagram126FIGURE 16-4: Simplified Block Diagram of Enhanced PWM Mode127Register 16-1: CCPxCON: CCPx Control Register (Standard CCP Modules)128Register 16-2: CCP1CON: ECCP1 Control Register (ECCP Modules Only)(1)129Register 16-3: ECCP1AS: ECCP1 Auto-Shutdown Control Register(1)130Register 16-4: ECCP1DEL: ECCP1 Enhanced PWM Control Register(1)131Register 16-5: PSTR1CON: Pulse Steering Control Register for ECCP1(1)132Register 16-6: CCPTMRS0: CCP Timer Select Control Register 0(1)13317.0 Master Synchronous Serial Port (MSSP)13517.1 I/O Pin Configuration for SPI135FIGURE 17-1: MSSP Block Diagram (SPI Mode)136FIGURE 17-2: SPI Master/Slave Connection136FIGURE 17-3: MSSP Block Diagram (I2C™ Mode)137FIGURE 17-4: MSSP Block Diagram (I2C™ Master Mode)137Register 17-1: SSPxSTAT: MSSPx Status Register (SPI Mode)138Register 17-2: SSPxSTAT: MSSPx Status Register (I2C™ Mode)139Register 17-3: SSPxCON1: MSSPx Control Register 1 (SPI Mode)141Register 17-4: SSPxCON1: MSSPx Control Register 1 (I2C™ Mode)142Register 17-5: SSPxCON2: MSSPx Control Register 2 (I2C™ Mode)143Register 17-6: SSPxCON3: MSSPx Control Register 3 (SPI Mode)144Register 17-7: SSPxCON3: MSSPx Control Register 3 (I2C™ Mode)145Register 17-8: SSPxADD: MSSPx Slave Address/Baud Rate Generator Register146Register 17-9: SSPxMSK: I2C Slave Address Mask Register146Register 17-10: PADCFG1: Pad Configuration Control Register14718.0 Universal Asynchronous Receiver Transmitter (UART)149FIGURE 18-1: UART Simplified Block Diagram14918.1 UART Baud Rate Generator (BRG)150EQUATION 18-1: UART Baud Rate with BRGH = 0(1)150EQUATION 18-2: UART Baud Rate with BRGH = 1(1)150EXAMPLE 18-1: Baud Rate Error Calculation (BRGH = 0)(1)15018.2 Transmitting in 8-Bit Data Mode15118.3 Transmitting in 9-Bit Data Mode15118.4 Break and Sync Transmit Sequence15118.5 Receiving in 8-Bit or 9-Bit Data Mode15118.6 Operation of UxCTS and UxRTS Control Pins15118.7 Infrared Support15118.7.1 External IrDA Support – IrDA Clock Output15118.7.2 Built-in IrDA Encoder and Decoder151Register 18-1: UxMODE: UARTx Mode Register152Register 18-2: UxSTA: UARTx Status and Control Register15419.0 10-Bit High-Speed A/D Converter157FIGURE 19-1: 10-Bit High-Speed A/D Converter Block Diagram158Register 19-1: AD1CON1: A/D Control Register 1159Register 19-2: AD1CON2: A/D Control Register 2160Register 19-3: AD1CON3: A/D Control Register 3161Register 19-4: AD1CHS: A/D Input Select Register162Register 19-5: AD1CSSL: A/D Input Scan Select Register163Register 19-6: ANCFG: Analog Input Configuration register163EQUATION 19-1: A/D Conversion Clock Period(1)164FIGURE 19-2: 10-bit A/D Converter Analog Input Model164FIGURE 19-3: A/D Transfer Function16520.0 Comparator Module167FIGURE 20-1: Comparator Module Block Diagram167FIGURE 20-2: Individual Comparator Configurations168Register 20-1: CMxCON: Comparator x Control Registers169Register 20-2: CMSTAT: Comparator Module Status Register17021.0 Comparator Voltage Reference17121.1 Configuring the Comparator Voltage Reference171FIGURE 21-1: Comparator Voltage Reference Block Diagram171Register 21-1: CVRCON: Comparator Voltage Reference Control Register17222.0 High/Low-Voltage Detect (HLVD)173FIGURE 22-1: High/Low-Voltage Detect (HLVD) Module Block Diagram173Register 22-1: HLVDCON: High/Low-Voltage Detect Control Register17423.0 Special Features17523.1 Configuration Bits175TABLE 23-1: CONFIGURATION Registers LOCATIONS175Register 23-1: FBS: Boot Segment Configuration Register176Register 23-2: FGS: General Segment Configuration Register176Register 23-3: FoscSEL: Oscillator Selection Configuration Register177Register 23-4: Fosc: Oscillator Configuration Register178Register 23-5: FWDT: Watchdog Timer Configuration Register179Register 23-6: FPOR: Reset Configuration Register180Register 23-7: FICD: In-Circuit Debugger Configuration Register18123.2 Unique ID181Register 23-8: DEVID: Device ID Register182Register 23-9: DEVREV: Device Revision Register18323.3 Watchdog Timer (WDT)18423.3.1 Windowed Operation18423.3.2 Control Register184FIGURE 23-1: WDT Block Diagram18423.4 Program Verification and Code Protection18523.5 In-Circuit Serial Programming18523.6 In-Circuit Debugger18524.0 Development Support18724.1 MPLAB Integrated Development Environment Software18724.2 MPLAB C Compilers for Various Device Families18824.3 HI-TECH C for Various Device Families18824.4 MPASM Assembler18824.5 MPLINK Object Linker/ MPLIB Object Librarian18824.6 MPLAB Assembler, Linker and Librarian for Various Device Families18824.7 MPLAB SIM Software Simulator18924.8 MPLAB REAL ICE In-Circuit Emulator System18924.9 MPLAB ICD 3 In-Circuit Debugger System18924.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express18924.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express19024.12 MPLAB PM3 Device Programmer19024.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits19025.0 Instruction Set Summary191TABLE 25-1: Symbols Used in Opcode Descriptions192TABLE 25-2: Instruction Set Overview19326.0 Electrical Characteristics199Absolute Maximum Ratings(†)19926.1 DC Characteristics200FIGURE 26-1: PIC24F16KL402 Family voltage-frequency graph (industrial)200TABLE 26-1: Thermal Operating Conditions200TABLE 26-2: Thermal Packaging Characteristics200TABLE 26-3: DC Characteristics: Temperature and Voltage Specifications201TABLE 26-4: High/Low–Voltage Detect Characteristics202TABLE 26-5: BOR Trip Points202TABLE 26-6: DC Characteristics: Operating Current (Idd)*203TABLE 26-7: DC Characteristics: Idle Current (Iidle)*203TABLE 26-8: DC Characteristics: Power-Down Current (Ipd)204TABLE 26-9: DC Characteristics: Power-Down Current (Ipd)204TABLE 26-10: DC Characteristics: I/O Pin Input Specifications205TABLE 26-11: DC Characteristics: I/O Pin Output Specifications206TABLE 26-12: DC Characteristics: Program Memory206TABLE 26-13: DC Characteristics: Data EEPROM Memory207TABLE 26-14: DC Specifications: Comparator207TABLE 26-15: DC Specifications: Comparator Voltage Reference s20726.2 AC Characteristics and Timing Parameters208TABLE 26-16: Temperature and Voltage Specifications – AC208FIGURE 26-2: Load Conditions for Device Timing Specifications208TABLE 26-17: Capacitive Loading Requirements on Output Pins208FIGURE 26-3: External Clock Timing209TABLE 26-18: External Clock Timing Requirements209TABLE 26-19: PLL Clock Timing Specifications210TABLE 26-20: Internal RC Oscillator Accuracy210TABLE 26-21: Internal RC Oscillator Specifications210FIGURE 26-4: CLKO and I/O Timing Characteristics211TABLE 26-22: CLKO and I/O Timing Requirements211TABLE 26-23: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-Up Timer, and Brown-Out Reset Timing Requirements212TABLE 26-24: Comparator Timings212TABLE 26-25: Comparator Voltage Reference Settling Time Specifications212FIGURE 26-5: Capture/Compare/PWM Timings (ECCP1, ECCP2 Modules)213TABLE 26-26: Capture/Compare/PWM Requirements (ECCP1, ECCP2 Modules)213FIGURE 26-6: Example SPI Master Mode Timing (CKE = 0)214TABLE 26-27: Example SPI Mode Requirements (Master Mode, Cke = 0)214FIGURE 26-7: Example SPI Master Mode Timing (CKE = 1)215TABLE 26-28: Example SPI Mode Requirements (Master Mode, CKE = 1)215FIGURE 26-8: Example SPI Slave Mode Timing (CKE = 0)216TABLE 26-29: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)216FIGURE 26-9: Example SPI Slave Mode Timing (CKE = 1)217TABLE 26-30: Example SPI Slave Mode Requirements (CKE = 1)217FIGURE 26-10: I2C™ Bus Start/Stop Bits Timing218TABLE 26-31: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)218FIGURE 26-11: I2C™ Bus Data Timing218TABLE 26-32: I2C™ Bus Data Requirements (Slave Mode)219FIGURE 26-12: MSSP I2C™ Bus Start/Stop Bits Timing Waveforms220TABLE 26-33: I2C™ Bus Start/Stop Bits Requirements (Master Mode)220FIGURE 26-13: MSSP I2C™ Bus Data Timing221TABLE 26-34: I2C™ Bus Data Requirements (Master Mode)221TABLE 26-35: A/D Module Specifications222TABLE 26-36: A/D Conversion TiminG Requirements(1)22327.0 Packaging Information22527.1 Package Marking Information22527.2 Package Details228Appendix A: Revision History249Revision A (September 2011)249Revision B (November 2011)249Appendix B: Migrating from PIC18/PIC24 to PIC24F16KL402249TABLE B-1: Table B-1: PIC24F16KL402 Peripheral Module Originating Architecture249INDEX251The Microchip Web Site255Customer Change Notification Service255Customer Support255Reader Response256Product Identification System257Worldwide Sales and Service260Размер: 3,2 МБСтраницы: 260Язык: EnglishПросмотреть
