사용자 설명서차례COVER1FEATURES1ORDERING INFORMATION2FUNCTION OVERVIEW2PIN CONFIGURATION (TOP VIEW)3BLOCK DIAGRAM51. PINS111.1 PIN FUNCTIONS111.2 EQUIVALENT CIRCUITS OF THE PINS142. PROGRAM MEMORY (ROM)182.1 CONFIGURATION OF PROGRAM MEMORY182.2 FUNCTIONS OF PROGRAM MEMORY192.3 PROGRAM FLOW192.4 BRANCHING A PROGRAM202.5 SUBROUTINE222.6 TABLE REFERENCE242.7 NOTES ON USING THE BRANCH INSTRUCTION AND SUBROUTINE CALL INSTRUCTION243. PROGRAM COUNTER (PC)254. STACK264.1 COMPONENTS264.2 STACK POINTER (SP)264.3 ADDRESS STACK REGISTERS (ASRS)274.4 INTERRUPT STACK REGISTERS275. DATA MEMORY (RAM)295.1 STRUCTURE OF DATA MEMORY295.2 FUNCTIONS OF DATA MEMORY345.3 NOTES ON USING DATA MEMORY386. GENERAL-PURPOSE REGISTER (GR)406.1 STRUCTURE OF THE GENERAL-PURPOSE REGISTER406.2 FUNCTION OF THE GENERAL-PURPOSE REGISTER406.3 ADDRESS GENERATION FOR GENERAL-PURPOSE REGISTER AND DATA MEMORY IN INDIVIDUAL INSTRUCTIONS426.4 NOTES ON USING THE GENERAL-PURPOSE REGISTER467. ARITHMETIC LOGIC UNIT (ALU) BLOCK487.1 OVERVIEW487.2 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK497.3 ALU OPERATIONS497.4 NOTES ON USING THE ALU538. SYSTEM REGISTER (SYSREG)548.1 ADDRESS REGISTER (AR)558.2 WINDOW REGISTER (WR)558.3 BANK REGISTER (BANK)568.4 MEMORY POINTER ENABLE FLAG (MPE)568.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP)578.6 GENERAL-PURPOSE REGISTER POINTER (RP)668.7 PROGRAM STATUS WORD (PSWORD)669. REGISTER FILE (RF)679.1 IDCDMAEN (00H, b1)759.2 SP (01H)759.3 CE (07H, b0)769.4 SERIAL INTERFACE MODE REGISTER (08H)769.5 BTM0MD (09H)779.6 INTVSYN (0FH, b2)779.7 INTNC (0FH, b0)789.8 HORIZONTAL SYNCHRONIZING SIGNAL COUNTER CONTROL (11H, 12H)789.9 PLL REFERENCE MODE SELECTION REGISTER (13H)799.10 SETTING OF INTNC PIN ACCEPTANCE PULSE WIDTH (15H)799.11 TIMER CARRY (17H)809.12 SERIAL INTERFACE WAIT CONTROL (18H)809.13 IEGNC (1FH)809.14 A/D CONVERTOR CONTROL (21H)819.15 PLL UNLOCK FLIP-FLOP JUDGE REGISTER (22H)819.16 PORT1C I/O SETTING (27H)829.17 SERIAL I/O0 STATUS REGISTER (28H)829.18 INTERRUPT PERMISSION FLAG (2FH)839.19 CROM BANK SELECTION (30H)839.20 IDCEN (31H)849.21 PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H)849.22 P1BBIOn (35H)859.23 P0BBIOn (36H)859.24 P0ABIOn (37H)869.25 SETTING OF INTERRUPT REQUEST GENERATION TIMING IN SERIAL INTERFACE MODE (38H)869.26 SHIFT CLOCK FREQUENCY SETTING (39H)879.27 IRQNC (3FH)8710. DATA BUFFER (DBF)8810.1 DATA BUFFER STRUCTURE8810.2 FUNCTIONS OF DATA BUFFER9010.3 DATA BUFFER AND TABLE REFERENCING9110.4 DATA BUFFER AND PERIPHERAL HARDWARE9310.5 DATA BUFFER AND PERIPHERAL REGISTERS9710.6 PRECAUTIONS WHEN USING DATA BUFFERS10411. INTERRUPT10611.1 INTERRUPT BLOCK CONFIGURATION10611.2 INTERRUPT FUNCTION10811.3 INTERRUPT ACCEPTANCE11111.4 OPERATIONS AFTER INTERRUPT ACCEPTANCE11611.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE11611.6 INTERRUPT PROCESSING ROUTINE11711.7 EXTERNAL INTERRUPTS (INTNC PIN, V SYNC# PIN)12111.8 INTERNAL INTERRUPT (TIMER, SERIAL INTERFACE)12311.9 MULTIPLE INTERRUPTS12412. TIMER13312.1 TIMER CONFIGURATION13312.2 TIMER FUNCTIONS13412.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF)13612.4 CAUTIONS IN USING THE TIMER CARRY FF14112.5 TIMER INTERRUPT14712.6 CAUTIONS IN USING THE TIMER INTERRUPT15113. STANDBY15313.1 STANDBY BLOCK CONFIGURATION15313.2 STANDBY FUNCTION15413.3 DEVICE OPERATION MODE SPECIFIED AT THE CE PIN15513.4 HALT FUNCTION15613.5 CLOCK STOP FUNCTION16413.6 OPERATION OF THE DEVICE AT A HALT OR CLOCK STOP16714. RESET17114.1 RESET BLOCK CONFIGURATION17114.2 RESET FUNCTION17214.3 CE RESET17314.4 POWER-ON RESET17714.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET18014.6 POWER FAILURE DETECTION18415. GENERAL-PURPOSE PORT18915.1 CONFIGURATION AND CLASSIFICATION OF GENERAL-PURPOSE PORT18915.2 FUNCTIONS OF GENERAL-PURPOSE PORTS19115.3 GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C)19415.4 GENERAL-PURPOSE INPUT PORT (P0D)19815.5 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A)19916. SERIAL INTERFACE20116.1 SERIAL INTERFACE MODE REGISTER20116.2 CLOCK COUNTER20616.3 STATUS REGISTER20716.4 WAIT REGISTER20916.5 PRESETTABLE SHIFT REGISTER (PSR)21416.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD)21516.7 SHIFT CLOCK FREQUENCY REGISTER (SIO0CK)21617. D/A CONVERTER21717.1 PWM PINS21718. PLL FREQUENCY SYNTHESIZER21918.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION21918.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK22018.3 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER22118.4 REFERENCE FREQUENCY GENERATOR (RFG)22318.5 PHASE COMPARATOR ( PHI-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK22518.6 PLL DISABLE MODE23118.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER23219. A/D CONVERTER23319.1 PRINCIPLE OF OPERATION23319.2 D/A CONVERTER CONFIGURATION23419.3 REFERENCE VOLTAGE SETTING REGISTER (ADCR)23519.4 COMPARISON REGISTER (ADCCMP)23519.5 ADC PIN SELECT REGISTER (ADCCHn)23619.6 EXAMPLE OF A/D CONVERSION PROGRAM23720. IMAGE DISPLAY CONTROLLER24020.1 SPECIFICATION OVERVIEW AND RESTRICTIONS24020.2 DIRECT MEMORY ACCESS24320.3 IDC ENABLE FLAG24520.4 VRAM24620.5 CHARACTER ROM25520.6 BLANK, R, G, AND B PINS26320.7 SPECIFYING THE DISPLAY START POSITION26420.8 SAMPLE PROGRAMS26821. HORIZONTAL SYNC SIGNAL COUNTER27421.1 HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION27421.2 GATE CONTROL REGISTER (HSCGT)27521.3 HSYNC COUNTER (HSC)27621.4 EXAMPLE OF USING THE HORIZONTAL SYNC SIGNAL27622. INSTRUCTION SETS27722.1 OUTLINE OF INSTRUCTION SETS27722.2 INSTRUCTIONS27822.3 LIST OF INSTRUCTION SETS27922.4 BUILT-IN MACRO INSTRUCTIONS28123. RESERVED SYMBOLS FOR ASSEMBLER28223.1 SYSTEM REGISTER28223.2 DATA BUFFER28223.3 PORT REGISTER28323.4 REGISTER FILES28423.5 PERIPHERAL HARDWARE REGISTER28623.6 OTHERS28624. ELECTRICAL CHARACTERISTICS28725. PACKAGE DRAWINGS28926. RECOMMENDED SOLDERING CONDITIONS291APPENDIX DEVELOPMENT TOOLS292크기: 1.38메가바이트페이지: 296Language: English매뉴얼 열기