Manuais de utilizador para NEC PD17062

índice analítico

• COVER

  1
• FEATURES

  1
• ORDERING INFORMATION

  2
• FUNCTION OVERVIEW

  2
• PIN CONFIGURATION (TOP VIEW)

  3
• BLOCK DIAGRAM

  5
• 1. PINS

  11
  • 1.1 PIN FUNCTIONS

    11
  • 1.2 EQUIVALENT CIRCUITS OF THE PINS

    14
• 2. PROGRAM MEMORY (ROM)

  18
  • 2.1 CONFIGURATION OF PROGRAM MEMORY

    18
  • 2.2 FUNCTIONS OF PROGRAM MEMORY

    19
  • 2.3 PROGRAM FLOW

    19
  • 2.4 BRANCHING A PROGRAM

    20
  • 2.5 SUBROUTINE

    22
  • 2.6 TABLE REFERENCE

    24
  • 2.7 NOTES ON USING THE BRANCH INSTRUCTION AND SUBROUTINE CALL INSTRUCTION

    24
• 3. PROGRAM COUNTER (PC)

  25
• 4. STACK

  26
  • 4.1 COMPONENTS

    26
  • 4.2 STACK POINTER (SP)

    26
  • 4.3 ADDRESS STACK REGISTERS (ASRS)

    27
  • 4.4 INTERRUPT STACK REGISTERS

    27
• 5. DATA MEMORY (RAM)

  29
  • 5.1 STRUCTURE OF DATA MEMORY

    29
  • 5.2 FUNCTIONS OF DATA MEMORY

    34
  • 5.3 NOTES ON USING DATA MEMORY

    38
• 6. GENERAL-PURPOSE REGISTER (GR)

  40
  • 6.1 STRUCTURE OF THE GENERAL-PURPOSE REGISTER

    40
  • 6.2 FUNCTION OF THE GENERAL-PURPOSE REGISTER

    40
  • 6.3 ADDRESS GENERATION FOR GENERAL-PURPOSE REGISTER AND DATA MEMORY IN INDIVIDUAL INSTRUCTIONS

    42
  • 6.4 NOTES ON USING THE GENERAL-PURPOSE REGISTER

    46
• 7. ARITHMETIC LOGIC UNIT (ALU) BLOCK

  48
  • 7.1 OVERVIEW

    48
  • 7.2 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK

    49
  • 7.3 ALU OPERATIONS

    49
  • 7.4 NOTES ON USING THE ALU

    53
• 8. SYSTEM REGISTER (SYSREG)

  54
  • 8.1 ADDRESS REGISTER (AR)

    55
  • 8.2 WINDOW REGISTER (WR)

    55
  • 8.3 BANK REGISTER (BANK)

    56
  • 8.4 MEMORY POINTER ENABLE FLAG (MPE)

    56
  • 8.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP)

    57
  • 8.6 GENERAL-PURPOSE REGISTER POINTER (RP)

    66
  • 8.7 PROGRAM STATUS WORD (PSWORD)

    66
• 9. REGISTER FILE (RF)

  67
  • 9.1 IDCDMAEN (00H, b1)

    75
  • 9.2 SP (01H)

    75
  • 9.3 CE (07H, b0)

    76
  • 9.4 SERIAL INTERFACE MODE REGISTER (08H)

    76
  • 9.5 BTM0MD (09H)

    77
  • 9.6 INTVSYN (0FH, b2)

    77
  • 9.7 INTNC (0FH, b0)

    78
  • 9.8 HORIZONTAL SYNCHRONIZING SIGNAL COUNTER CONTROL (11H, 12H)

    78
  • 9.9 PLL REFERENCE MODE SELECTION REGISTER (13H)

    79
  • 9.10 SETTING OF INTNC PIN ACCEPTANCE PULSE WIDTH (15H)

    79
  • 9.11 TIMER CARRY (17H)

    80
  • 9.12 SERIAL INTERFACE WAIT CONTROL (18H)

    80
  • 9.13 IEGNC (1FH)

    80
  • 9.14 A/D CONVERTOR CONTROL (21H)

    81
  • 9.15 PLL UNLOCK FLIP-FLOP JUDGE REGISTER (22H)

    81
  • 9.16 PORT1C I/O SETTING (27H)

    82
  • 9.17 SERIAL I/O0 STATUS REGISTER (28H)

    82
  • 9.18 INTERRUPT PERMISSION FLAG (2FH)

    83
  • 9.19 CROM BANK SELECTION (30H)

    83
  • 9.20 IDCEN (31H)

    84
  • 9.21 PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H)

    84
  • 9.22 P1BBIOn (35H)

    85
  • 9.23 P0BBIOn (36H)

    85
  • 9.24 P0ABIOn (37H)

    86
  • 9.25 SETTING OF INTERRUPT REQUEST GENERATION TIMING IN SERIAL INTERFACE MODE (38H)

    86
  • 9.26 SHIFT CLOCK FREQUENCY SETTING (39H)

    87
  • 9.27 IRQNC (3FH)

    87
• 10. DATA BUFFER (DBF)

  88
  • 10.1 DATA BUFFER STRUCTURE

    88
  • 10.2 FUNCTIONS OF DATA BUFFER

    90
  • 10.3 DATA BUFFER AND TABLE REFERENCING

    91
  • 10.4 DATA BUFFER AND PERIPHERAL HARDWARE

    93
  • 10.5 DATA BUFFER AND PERIPHERAL REGISTERS

    97
  • 10.6 PRECAUTIONS WHEN USING DATA BUFFERS

    104
• 11. INTERRUPT

  106
  • 11.1 INTERRUPT BLOCK CONFIGURATION

    106
  • 11.2 INTERRUPT FUNCTION

    108
  • 11.3 INTERRUPT ACCEPTANCE

    111
  • 11.4 OPERATIONS AFTER INTERRUPT ACCEPTANCE

    116
  • 11.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE

    116
  • 11.6 INTERRUPT PROCESSING ROUTINE

    117
  • 11.7 EXTERNAL INTERRUPTS (INTNC PIN, V SYNC# PIN)

    121
  • 11.8 INTERNAL INTERRUPT (TIMER, SERIAL INTERFACE)

    123
  • 11.9 MULTIPLE INTERRUPTS

    124
• 12. TIMER

  133
  • 12.1 TIMER CONFIGURATION

    133
  • 12.2 TIMER FUNCTIONS

    134
  • 12.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF)

    136
  • 12.4 CAUTIONS IN USING THE TIMER CARRY FF

    141
  • 12.5 TIMER INTERRUPT

    147
  • 12.6 CAUTIONS IN USING THE TIMER INTERRUPT

    151
• 13. STANDBY

  153
  • 13.1 STANDBY BLOCK CONFIGURATION

    153
  • 13.2 STANDBY FUNCTION

    154
  • 13.3 DEVICE OPERATION MODE SPECIFIED AT THE CE PIN

    155
  • 13.4 HALT FUNCTION

    156
  • 13.5 CLOCK STOP FUNCTION

    164
  • 13.6 OPERATION OF THE DEVICE AT A HALT OR CLOCK STOP

    167
• 14. RESET

  171
  • 14.1 RESET BLOCK CONFIGURATION

    171
  • 14.2 RESET FUNCTION

    172
  • 14.3 CE RESET

    173
  • 14.4 POWER-ON RESET

    177
  • 14.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET

    180
  • 14.6 POWER FAILURE DETECTION

    184
• 15. GENERAL-PURPOSE PORT

  189
  • 15.1 CONFIGURATION AND CLASSIFICATION OF GENERAL-PURPOSE PORT

    189
  • 15.2 FUNCTIONS OF GENERAL-PURPOSE PORTS

    191
  • 15.3 GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C)

    194
  • 15.4 GENERAL-PURPOSE INPUT PORT (P0D)

    198
  • 15.5 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A)

    199
• 16. SERIAL INTERFACE

  201
  • 16.1 SERIAL INTERFACE MODE REGISTER

    201
  • 16.2 CLOCK COUNTER

    206
  • 16.3 STATUS REGISTER

    207
  • 16.4 WAIT REGISTER

    209
  • 16.5 PRESETTABLE SHIFT REGISTER (PSR)

    214
  • 16.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD)

    215
  • 16.7 SHIFT CLOCK FREQUENCY REGISTER (SIO0CK)

    216
• 17. D/A CONVERTER

  217
  • 17.1 PWM PINS

    217
• 18. PLL FREQUENCY SYNTHESIZER

  219
  • 18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION

    219
  • 18.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK

    220
  • 18.3 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER

    221
  • 18.4 REFERENCE FREQUENCY GENERATOR (RFG)

    223
  • 18.5 PHASE COMPARATOR ( PHI-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK

    225
  • 18.6 PLL DISABLE MODE

    231
  • 18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER

    232
• 19. A/D CONVERTER

  233
  • 19.1 PRINCIPLE OF OPERATION

    233
  • 19.2 D/A CONVERTER CONFIGURATION

    234
  • 19.3 REFERENCE VOLTAGE SETTING REGISTER (ADCR)

    235
  • 19.4 COMPARISON REGISTER (ADCCMP)

    235
  • 19.5 ADC PIN SELECT REGISTER (ADCCHn)

    236
  • 19.6 EXAMPLE OF A/D CONVERSION PROGRAM

    237
• 20. IMAGE DISPLAY CONTROLLER

  240
  • 20.1 SPECIFICATION OVERVIEW AND RESTRICTIONS

    240
  • 20.2 DIRECT MEMORY ACCESS

    243
  • 20.3 IDC ENABLE FLAG

    245
  • 20.4 VRAM

    246
  • 20.5 CHARACTER ROM

    255
  • 20.6 BLANK, R, G, AND B PINS

    263
  • 20.7 SPECIFYING THE DISPLAY START POSITION

    264
  • 20.8 SAMPLE PROGRAMS

    268
• 21. HORIZONTAL SYNC SIGNAL COUNTER

  274
  • 21.1 HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION

    274
  • 21.2 GATE CONTROL REGISTER (HSCGT)

    275
  • 21.3 HSYNC COUNTER (HSC)

    276
  • 21.4 EXAMPLE OF USING THE HORIZONTAL SYNC SIGNAL

    276
• 22. INSTRUCTION SETS

  277
  • 22.1 OUTLINE OF INSTRUCTION SETS

    277
  • 22.2 INSTRUCTIONS

    278
  • 22.3 LIST OF INSTRUCTION SETS

    279
  • 22.4 BUILT-IN MACRO INSTRUCTIONS

    281
• 23. RESERVED SYMBOLS FOR ASSEMBLER

  282
  • 23.1 SYSTEM REGISTER

    282
  • 23.2 DATA BUFFER

    282
  • 23.3 PORT REGISTER

    283
  • 23.4 REGISTER FILES

    284
  • 23.5 PERIPHERAL HARDWARE REGISTER

    286
  • 23.6 OTHERS

    286
• 24. ELECTRICAL CHARACTERISTICS

  287
• 25. PACKAGE DRAWINGS

  289
• 26. RECOMMENDED SOLDERING CONDITIONS

  291
• APPENDIX DEVELOPMENT TOOLS

  292