STMicroelectronics Demonstration board based on the TSC102 STEVAL-ISQ010V1 사용자 매뉴얼

차례

• 1 Application schematic and pin description

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  • Figure 1. Application schematics

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  • Table 1. Pin description

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• 2 Absolute maximum ratings and operating conditions

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  • Table 2. Absolute maximum ratings

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  • Table 3. Operating conditions

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• 3 Electrical characteristics

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  • Table 4. Supply

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  • Table 5. Current sensing amplifier input stage

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  • Table 6. Current sensing amplifier output stage

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  • Table 7. Current sensing amplifier frequency response

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  • Table 8. Current sensing amplifier noise

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  • Table 9. Signal conditioning amplifier

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• 4 Electrical characteristics curves: current sense amplifier

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  • Figure 2. Output voltage vs. Vsense

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  • Figure 3. A1 pin voltage accuracy vs. Vsense

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  • Figure 4. Supply current vs. supply voltage

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  • Figure 5. Supply current vs. Vsense

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  • Figure 6. Vp pin input bias current vs. Vsense

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  • Figure 7. Vm pin input bias current vs. Vsense

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  • Figure 8. Output stage low-state saturation voltage versus output current (Vsense = -1 V)

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  • Figure 9. Output stage high-state saturation voltage versus output current (Vsense = +1 V)

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  • Figure 10. Output stage load regulation

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  • Figure 11. Step response

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  • Figure 12. Bode diagram

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  • Figure 13. Power supply rejection ratio

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• 5 Electrical characteristics curves: signal conditioning amplifier

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  • Figure 14. Input offset voltage versus input common-mode voltage

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  • Figure 15. Input offset voltage versus supply voltage (Vicm = Vcc/2)

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  • Figure 16. Output current versus output voltage

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  • Figure 17. Bode diagram (Vout = Vcc/2, RL = 10 kW, Cload = 100 pF)

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• 6 Parameter definitions

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  • 6.1 Common-mode rejection ratio (CMR)

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  • 6.2 Supply voltage rejection ratio (SVR)

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  • 6.3 Gain (Av) and input offset voltage (Vos)

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    • Figure 18. Va1 versus Vsense characteristics: detail for low Vsense values

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  • 6.4 Output voltage drift versus temperature

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    • Figure 19. Output voltage drift versus temperature

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  • 6.5 Output voltage accuracy

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    • Figure 20. Va1 vs. Vsense theoretical and actual characteristics

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• 7 Application information

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  • Figure 21. Typical application schematic

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  • Figure 22. Gain higher than 20

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  • Figure 23. Gain lower than 20

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  • Figure 24. Overcurrent protection

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  • Figure 25. First-order low-pass filter

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  • Figure 26. Second-order low-pass filter

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• 8 Package information

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  • 8.1 TSSOP8 package information

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    • Figure 27. TSSOP8 package mechanical drawing

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    • Table 10. TSSOP8 package mechanical data

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  • 8.2 SO8 package information

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    • Figure 28. SO8 package mechanical drawing

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    • Table 11. SO8 package mechanical data

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• 9 Ordering information

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  • Table 12. Order codes

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• 10 Revision history

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  • Table 13. Document revision history

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