Renesas SH7709S Manual Do Utilizador

Rev. 5.00, 09/03, page 87 of 760

*

Reset

Aborted

Power-on reset

1

—

H'A00000000 —

Manual reset

1

—

H'A00000000 —

UDI reset

1

—

H'A00000000 —

Aborted
and retried

CPU address error
(instruction access)

2

1

—

H'00000100

General
exception
events

TLB miss

2

2

—

H'00000400

TLB invalid
(instruction access)

2

3

—

H'00000100

TLB protection
violation (instruction
access)

2

4

—

H'00000100

General illegal
instruction exception

2

5

—

H'00000100

Illegal slot instruction
exception

2

5

—

H'00000100

CPU address error
(data access)

2

6

—

H'00000100

TLB miss (data access
not in repeat loop)

2

7

—

H'00000400

TLB invalid (data
access)

2

8

—

H'00000100

TLB protection
violation (data access)

2

9

—

H'00000100

Initial page write

2

10

—

H'00000100

Completed Unconditional trap

(TRAPA instruction)

2

5

—

H'00000100

User breakpoint trap

2

n

*

2

—

H'00000100

DMA address error

2

—

—

H'00000100

Completed Nonmaskable interrupt 3

—

—

H'00000600

General
interrupt
requests

External hardware
interrupt

4

*

3

—

—

H'00000600

UDI interrupt

4

*

3

—

—

H'00000600

Notes: 1. Priorities are indicated from high to low, 1 being the highest and 4 the lowest.

2. The user defines the break point traps. 1 is a break point before instruction execution

and 11 is a break point after instruction execution. For an operand break point, use 11.

3. Use software to specify relative priorities of external hardware interrupts and peripheral

module interrupts (see section 6, Interrupt Controller (INTC)).