Renesas SH7709S Manual Do Utilizador
Rev. 5.00, 09/03, page 89 of 760
IF
Instruction n
ID
EX
MA
TLB miss (data access)
WB
IF
Instruction n + 1
Instruction n + 2
ID
EX
MA
TLB miss (instruction access)
WB
IF
ID
EX
MA
RIE (reserved instruction exception)
WB
Pipeline Sequence:
TLB miss (instruction n)
Re-execution of instruction n
1
2
3
TLB miss (instruction n + 1)
Re-execution of instruction n + 1
RIE (instruction n + 2)
IF
ID
EX
MA
WB
ID
EX
MA
WB
= Instruction fetch
= Instruction decode
= Instruction execution
= Memory access
= Write back
= Instruction decode
= Instruction execution
= Memory access
= Write back
Handling Order:
Program Order:
TLB miss (instruction n+1)
TLB miss (instruction n) and general illegal instruction exception (instruction n + 2)
= simultaneous detection
= simultaneous detection
Detection Order:
Figure 4.2 Example of Acceptance Order of General Exceptions
All exceptions other than a reset are detected in the pipeline ID stage, and accepted at instruction
boundaries. However, an exception is not accepted between a delayed branch instruction and the
delay slot. A re-execution type exception detected in a delay slot is accepted before execution of
the delayed branch instruction. A completion type exception detected in a delayed branch
boundaries. However, an exception is not accepted between a delayed branch instruction and the
delay slot. A re-execution type exception detected in a delay slot is accepted before execution of
the delayed branch instruction. A completion type exception detected in a delayed branch