Renesas SH7709S Manual Do Utilizador

Renesas

Rev. 5.00, 09/03, page 126 of 760

Table 6.4

Interrupt Exception Handling Sources and Priority (IRQ Mode)

Interrupt Source

INTEVT Code
(INTEVT2 Code)

Interrupt
Priority
(Initial Value)

IPR (Bit
Numbers)

Priority
within IPR
Setting Unit

Default
Priority

NMI

H'1C0 (H'1C0)

16

—

—

High

UDI

H'5E0 (H'5E0)

15

—

—

IRQ

IRQ0

H'200–3C0

*

(H'600)

0–15 (0)

IPRC (3–0)

—

IRQ1

H'200–3C0

*

(H'620)

0–15 (0)

IPRC (7–4)

—

IRQ2

H'200–3C0

*

(H'640)

0–15 (0)

IPRC (11–8)

—

IRQ3

H'200–3C0

*

(H'660)

0–15 (0)

IPRC (15–12) —

IRQ4

H'200–3C0

*

(H'680)

0–15 (0)

IPRD (3–0)

—

IRQ5

H'200–3C0

*

(H'6A0)

0–15 (0)

IPRD (7–4)

—

PINT

PINT0–7

H'200–3C0

*

(H'700)

0–15 (0)

IPRD (15–12) —

PINT8–15

H'200–3C0

*

(H'720)

0–15 (0)

IPRD (11–8)

—

DMAC

DEI0

H'200–3C0

*

(H'800)

0–15 (0)

IPRE (15–12) High

DEI1

H'200–3C0

*

(H'820)

DEI2

H'200–3C0

*

(H'840)

DEI3

H'200–3C0

*

(H'860)

Low

IrDA

ERI1

H'200–3C0

*

(H'880)

0–15 (0)

IPRE (11–8)

High

RXI1

H'200–3C0

*

(H'8A0)

BRI1

H'200–3C0

*

(H'8C0)

TXI1

H'200–3C0

*

(H'8E0)

Low

SCIF

ERI2

H'200–3C0

*

(H'900)

0–15 (0)

IPRE (7–4)

High

RXI2

H'200–3C0

*

(H'920)

BRI2

H'200–3C0

*

(H'940)

TXI2

H'200–3C0

*

(H'960)

Low

ADC

ADI

H'200–3C0

*

(H'980)

0–15 (0)

IPRE (3–0)

—

TMU0

TUNI0

H'400 (H'400)

0–15 (0)

IPRA (15–12) —

TMU1

TUNI1

H'420 (H'420)

0–15 (0)

IPRA (11–8)

—

TMU2

TUNI2

H'440 (H'440)

0–15 (0)

IPRA (7–4)

High

TICPI2

H'460 (H'460)

Low

Low